Philip J. Cacharelis

A Reflective-mode PDLC Light Valve Display Technology

A silicon-based display technology was developed using a 0.8 μm EEPROM process flow [1] and a reflective-mode, polymer-dispersed-liquid-crystal (PDLC) cell in order to generate a high resolution light valve. The silicon backplane driver is coupled to the PDLC cell which is mounted directly on the die. Modifications to the EEPROM process frontend and optimization of a 3 layer metal backend were conducted based on the specific requirements of the light valve. The light valves were combined with optical beam-splitting and beamcombining prisms to enable full color projection displays. A prototype projector was assembled to demonstrate the technology approach.

Electron barrier height change and its influence on EEPROM cells

The effect of floating polysilicon doping on electron injection barrier height and therefore the PROGRAM/ERASE window of an electrically erasable programmable ROM (EEPROM) cell has been studied. The introduction of dopant and the concentration of electrically active sites at the floating-gate polysilicon/tunnel oxide interface influence the electron injection barrier height during cell ERASE operation. The electron injection barrier increases up to 250 meV upon degenerate doping of the floating-gate polysilicon electrode as measured by dark current-voltage characteristics. The application of these observations in this study is in the design and scaling of EEPROM cells.<<ETX>>

A single transistor electrically alterable cell

A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electron injection while erasing is performed via Fowler-Nordheim tunneling through a thin oxide (100-Å) region. The memory cell requires only one transistor because the write and erase voltages range between 15-20 and 25-30 V, respectively. The writeability of the cell is enhanced by the thin oxide region and dependent on the proximity of this region to the channel of the DMOS transistor.

A reflective-mode EEPROM-based silicon light-valve technology

— A single-crystal-silicon light-valve technology was created by optimizing a 0.8-mgr;m EEPROM process flow to satisfy the electrical and optical requirements of the light valves transducer, a polymer-dispersed liquid crystal (PDLC).

A Back - Biased 0.65 μm Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices

A high-speed back-biased CMOS EEPROM technology and its application to Programmable Logic Devices (PLDs) will be described. Several key features have allowed the fabrication of a next generation high performance EECMOS PLD; the use of two independent families of transistors for the high voltage programming and read paths, the application of back-bias and careful optimisation of a double-polysilicon EEPROM cell. A sub 7 ns EECMOS PLD is described.

A modular 1 mu m CMOS single polysilicon EPROM PLD technology

The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns. Snap-back has been identified as the major cause of program disturb.<<ETX>>