Michael J. Hart

The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance

The impact of plasma-induced damage on the speed performance of a field programmable gate array (FPGA) is presented. It was found that FPGA speed degradation induced by product reliability burn-in was directly related to a large negative threshold voltage (V/sub t/) shift of the surface channel PMOS induced by negative bias temperature (BT) stress. Such negative bias temperature instability (NBTI) in the PMOS was shown to be related to specific back-end plasma processing steps. An overall reduction in NBTI of the PMOSFET was observed when certain plasma processing steps were eliminated which in turn resulted in the reduction of FPGA performance degradation.

Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

The single-event response of Xilinx 20nm UltraScale Kintex FPGA is characterized using neutron, 64 MeV proton, thermal neutron and alpha foil irradiation sources. Single-event upset and multi-bits upset results are presented.

Impact of Temperature and Vcc Variation on 20nm Kintex UltraScale FPGAs Neutron Soft Error Rate

The single-event response vs. temperature and Vcc supply voltage of the 20nm Kintex UltraScale FPGA is characterized using a 64 MeV proton beam as proxy for atmospheric neutron. Single-event upset and multi-bit upset results are presented.

64 MeV proton single-event upset characterization of customer memory interface design on Xilinx XCKU040 FPGA

This paper examines the single-event upset response of a customer memory interface design on the Xilinx 20nm XCKU040 Field Programmable Gate Array (FPGA) irradiated with 64MeV proton source. Results for single-event upsets on configuration RAM (CRAM) cells are provided. The difference between architectural vulnerability factor (AVF) and design vulnerability factor (DVF) of the customer memory interface design is also discussed in this work.

Neutron, 64 MeV proton & alpha single-event characterization of Xilinx 16nm FinFET Zynq® UltraScale+™ MPSoC

This paper examines the single-event effect response of the Xilinx 16nm FinFET XCZU9EG Zynq® MPSoC irradiated with neutrons, 64 MeV protons and thermal neutrons sources. A 16nm FPGA-like test chip was also built for alpha foil testing. Results for single-event upsets on configuration RAM (CRAM) cells and block RAM (bRAM) cells are provided for the programmable logic. In addition, the 1st· Xilinx 16nm FinFET processor (PS) SEE results are also presented.

Latchup in bulk FinFET technology

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

Single-Event Upsets Characterization a Evaluation of Xilinx UltraScale™ Soft Error Mitigation (SEM IP) Tool

This paper examines the single-event upset response of the Xilinx UltraScale Soft Error Mitigation (SEM IP) software tool irradiated with a 64MeV proton source. The SEM SEU results are then compared to accelerated particle testing results for the Xilinx 20nm Kintex family, collected at LANSCE and Crocker, to evaluate its capability to detect & collect SEU accurately. Furthermore, Xilinx 20nm stacked silicon on interposer (SSI) technology SEU response is characterized. SEU and MBU results are presented.

Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification

Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.

FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification

Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre DRC design rule checking. Our proposed analytical model shows ∼50% increase of the electric field at the FinFET top compared to planar sidewalls. A higher electric field at the fin-top decreases gate oxide breakdown, reduces RX charged device model (CDM) immunity for the FinFET MPSoC, and brings the RX on par with the TX, CDM-wise.