Philip R. Moorby

User-Defined Primitives

Verilog provides a set of 26 gate level primitives for modeling the actual logic implementation of a digital system. From these primitives, presented in Chapter 4, larger structural models may be hierarchically described. This chapter presents an advanced method for extending the set of gate level primitives to include user-defined combinational, and level- and edge-sensitive sequential circuits.

Verilog -- A Tutorial Introduction

Digital systems are highly complex. At their most detailed level, they may consist of millions of elements, as would be the case if we viewed a system as a collection of logic gates or pass transistors. From a more abstract viewpoint, these elements may be grouped into a handful of functional components such as cache memories, floating point units, signal processors, or real-time controllers. Hardware description languages have evolved to aid in the design of systems with this large number of elements and wide range of electronic and logical abstractions.

Three Large Examples

MiniSim is a description of a very simplified gate level simulator. Only three primitives have been included: a nand gate, a D positive edge-triggered flip flop, and a wire that handles the full strength algebra that is used in Verilog. All primitive timing is unit delay, and a record is kept of the stimulus pattern number and simulation time within each pattern. Each primitive is limited to two inputs and one output that has a maximum fanout of two.

Behavioral Modeling Constructs

We now begin a more in-depth discussion of the constructs used to model the behavior of digital systems. These have been split into two groups. The first are statements that are, for the most part, similar to those found in programming languages: if-then-else, loops, etc. In the next chapter we take up the statements that are oriented toward modeling the concurrent nature of digital hardware.

Defining Gate Level Primitives

Verilog provides a set of 26 gate level primitives for modeling the actual logic implementation of a digital system. From these primitives, presented in Chapter 4, larger structural models may be hierarchically described. This chapter presents an advanced method for extending the set of gate level primitives to include user-defined combinational, and level- and edge-sensitive sequential circuits.

Concurrent Process Statements

Most of the behavioral modeling statements discussed to this point have been demonstrated using single process examples. These statements are part of the body of an always statement and are repetitively executed in sequential order. They may operate on values that are inputs or outputs of the module or on the module’s internal registers. In this chapter we present behavioral modeling statements that by their definition interact with activities external to the enclosing always. For instance, the wait statement waits for its expression to become TRUE as a result of a value being changed in another process. As in this case and the others to be presented here, the operation of the wait statement is dependent on the actions of concurrent processes in the system.

Two Large Examples

MiniSim is a description of a very simplified gate level simulator. Only three primitives have been included: a nand gate, a D positive edge-triggered flip flop, and a wire that handles the full strength algebra that is used in Verilog. All primitive timing is unit delay, and a record is kept of the stimulus pattern number and simulation time within each pattern. Each primitive is limited to two inputs and two outputs.