Donald E. Thomas

A model and methodology for hardware-software codesign

A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration on a testbed consisting of a commercial central processing unit (CPU), field-programmable gate arrays, and programmable interconnections. Design examples that illustrate how certain characteristics of system behavior and constraints suggest hardware or software implementation are presented. >

Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench

1. Introduction.- 1.1. Synthesis of Integrated Circuits.- 1.2 The System Architects Workbench.- 1.3 Contrasting Approaches to Synthesis.- 1.4. Historical Note.- 1.5. Overview of the Book.- 2. Design Representations and Synthesis.- 2.1 The Model of Design Representation.- 2.2. Behavioral Representations at the ALGORITHMIC Level.- 2.3. Behavioral and Structural Representations at the REGISTER-TRANSFER Level.- 2.4. Modeling ALGORITHMIC and RT Level Synthesis.- 2.6 Summary.- 3. Transformations.- 3.1. Vtbody Transformations.- 3.2. SELECT Transformations.- 3.3. Adding Processes To The Workbench.- 3.4. Process Creation.- 3.5. Pipestage Creation.- 3.6. Structural Transformations.- 3.7. Summary.- 4. Architectural Partitioning (APARTY).- 4.1. Architectural Partitioning.- 4.2. Previous Work: Clustering.- 4.3. Multi-Stage Clustering.- 4.4. Methodology.- 4.5. Guiding Other Synthesis Tools.- 4.6. A Partitioning Example.- 4.7. Summary.- 5. Control Step Scheduling (CSTEP).- 5.1. The Scheduling Problem.- 5.2. Related Work.- 5.3. The CSTEP Scheduling Approach.- 5.4. Scheduling Examples.- 5.5. Summary.- 6. Data Path Allocation (EMUCS).- 6.1. Other Data Path Allocators.- 6.2. EMUCS Overview.- 6.3. Initialization.- 6.4. Prebinding and Manual Binding.- 6.5. Automatic Binding.- 6.6. Post-Processing.- 6.7. Finish Up.- 6.9. Summary.- 7. Microprocessor Synthesis (SUGAR).- 7.1. Organization of SUGAR.- 7.2. Behavioral Transformations.- 7.3. Execution Unit Organization Analysis.- 7.4. Code Generation.- 7.5. Code Selection.- 7.6. Register and Bus Assignment.- 7.7. Phase Structure of SUGAR.- 7.8. Summary.- 8. Synthesis Results.- 8.1. Fifth Order Digital Elliptic Wave Filter.- 8.2. Kalman Filter.- 8.3. BTL310.- 8.4. MCS6502.- 8.5. MC68000.- 8.6. Summary.- 9. Correlating the Multilevel Design Representation (CORAL).- 9.1 Linking Design Representations.- 9.2 Applications.- 9.3 Summary.- 10. Observations and Future Work.- 10.1. Are The Two Synthesis Paths Different?.- 10.2. You Need More Than Synthesis.- 10.3. Algorithmic Level Synthesis.- 10.4. Logic Synthesis, Module Generation and Physical Design.- 10.5. Design Languages.- 10.6. Summary.- References.

The combination of scheduling, allocation, and mapping in a single algorithm

We present a single high level synthesis algorithm that schedules the operations of a data dependence graph, allocates the necessary hardware, and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph.

A design methodology and computer aids for digital VLSI systems

The current status of a research program at Carnegie-Mellon University aimed at the formulation of a hierarchical design methodology for digital VLSI circuits is described. In addition, this paper describes a set of computer aids which supports this methodology. One of the goals of this work is to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks. Another goal is to allow the designer to efficiently explore a number of design alternatives.

Architectural partitioning for system level synthesis of integrated circuits

APARTY is an architectural partitioning tool that uses a novel multistage clustering algorithm to extract the high level structure of an IC design by concentrating on area and interconnect considerations. Performance is addressed implicitly. APARTY works within the framework of the system architects workbench and can pass system-level structural information along to register-transfer level (RTL) tools to guide the completion of a data-path design. The multistage clustering algorithm and how it is used by APARTY to choose partitions are described. The system architects workbench and how architectural partitioning can be used to guide synthesis are also described. Results of using APARTY in the design process show improved register-transfer designs. In particular, the number of global routing wires is generally reduced by over 50% by following the partitioning scheme suggested by APARTY. >

Managing pipeline-reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

A Method of Automatic Data Path Synthesis

A method of automatically synthesizing data paths from a behavioral description has been developed. An initial implementation of this method, which is integrated into the Carnegie-Mellon University Design Automation system, is presented in this paper. Its principles of operation are explained and an evaluation of its performance is given. This method of automatic synthesis surpasses the performance of previous CMU-DA approaches. Further, a designer can use it in a semi-automatic fashion and complement its abilities with his expert insight.

Behavioral transformation for algorithmic level IC design

An attempt was made to define the algorithmic level of design (also known as the behavioral level) and to provide the designer with the means to explore various design issues. Within the framework of the System Architects Workbench, a new set of behavioral and structural transformations was developed to allow the interactive exploration of algorithmic-level design alternatives. A description is given of these transformations, and a set of examples is presented both to demonstrate the application of the transformations and to further illustrate their effects. >

Architectural Partitioning for System Level Design

Architectural partitioning is introduced as a new phase in system level synthesis. Architectural partitioning extracts high level structure from the behavior of an architecture. This paper describes the APARTY architectural partitioner, an automatic Architectural PARTYtioner that supports synthesis in the System Architects Workbench. APARTY uses a unique multi-stage clustering technique. Knowledge of the high level structure of an architecture aids synthesis tools in choosing a better design in terms of area. For one example, architectural partitioning reduced the number of wiring tracks in the final design by 20%.

A Model of Design Representation and Synthesis

To represent the increasingly complex designs being produced today, we have developed 1 a unified model of design representation that uses three hierarchical, non-isomorphic domains of description that can be coordinated to represent the entire design. Each of these domains contains multiple levels of abstraction; both the domains and the levels are described in detail in this paper. We then show how this model of design representation can be used as a model of design synthesis. It is hoped that this work will lead to a better understanding of design representation and its relationship to the synthesis process.