Philippe Benabes

A methodology for designing continuous-time sigma-delta modulators

A methodology for analysis and synthesis of lowpass sigma-delta (/spl Sigma//spl Delta/) converters is presented in this paper. This method permits to synthesize /spl Sigma//spl Delta/ modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of continuous-time model and using a discrete simulator which is more efficient than an analog simulator. Finally, a realistic design of a second-order /spl Sigma//spl Delta/ modulator with a compensation of the non ideal behavior of DAC is given. Moreover, simulation results show a good agreement with the theoretical bases.

22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS

Todays applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.

Optoelectronic interconnection technology in the HOLMS system

The High-Speed Optoelectronic Memory Systems (HOLMS) project, sponsored by the European Union Information Society Technology program, aims to make the use of board level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes. To demonstrate the potential of the technology, we develop a demonstrator system that addresses the most pressing problem of contemporary computer architecture, memory latency. This paper describes the key ideas and some preliminary results of the HOLMS projects focusing on electronic interconnection technology, in particular optoelectronic packaging issues.

Synthesis and Analysis of Sigma-Delta Modulators Employing Continuous-Time Filters

A methodology for analysis and synthesis of lowpass sigma-delta (ΣΔ) converters is presented in this paper. This method permits the synthesis of ΣΔ modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order ΣΔ modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.

Design and construction of an optoelectronic crossbar switch containing a terabit per second free-space optical interconnect

The completed detailed design and initial phases of construction of an optoelectronic crossbar demonstrator are presented. The experimental system uses hybrid very large scale integrated optoelectronics technology whereby InGaAs-based detectors and modulators are flip-chip bonded onto silicon integrated circuits. The system aims to demonstrate a 1-Tb/s aggregate data input/output to a single chip by means of free-space optics.

A digital piezoelectric accelerometer with sigma-delta servo technique

Abstract This paper presents the design and performance of a direct digital accelerometer using oversampling sigma-delta servo electronics. The measuring system, also called an ‘electromechanical sigma-delta modulator’, is based on a piezoelectric measuring cell integrated inside the first stage of a second-order sigma-delta modulator. The piezoelectric measuring cell has a new structure in order to realize the acceleration sensing and the servo-loop summer. The active material used in an inexpensive and versatile piezoelectric polymer, polyvinylidene fluoride (PVDF). The accelerometer aims at a working range of ± 1 g and eight-bit resolution. It is suited for vibration measurement.

A Manchester code generator running at 1 GHz

A new Manchester code generator designed at transistor level is presented in this paper. This generator uses 32 transistors and has the same complexity as a standard D flip-flop. It is intended to be used in a complex optical communication system. The main benefit of this design is to use a clock signal running at the same frequency as the data. Output changes on the rising edge and falling edge of the clock. Simulations results show a correct behavior up to 1 Gbit/s data rate with a 0.35 /spl mu/ CMOS technology within a commercial temperature range.

A multistage closed-loop sigma-delta modulator (MSCL)

A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model.

A Matlab based tool for bandpass continuous-time sigma-delta modulators design

A methodology for synthesis and analysis of bandpass sigma-delta (/spl Sigma//spl Delta/) converters has been developed and integrated in a Matlab toolbox. It allows the synthesis of /spl Sigma//spl Delta/ modulators with continuous time filters from discrete time topologies. The analysis method is based on the discretization of continuous-time models. It uses a discrete time simulator, more efficient than an analog simulator. All tools are included in a fully interactive, graphic and open framework in which user-developed modules can be added.

Bandpass Delta-Sigma modulators synthesis with high loop delay

A new analysis and synthesis method for continuous time bandpass Delta-Sigma (/spl Delta//spl Sigma/) modulators is presented in this paper. This method makes it possible to synthesize continuous bandpass /spl Delta//spl Sigma/ modulators from discrete time topologies and it takes into account DAC+ADC delay and rise time. Theoretically, high loop delay can be achieved and non-ideal DAC can be used without effect on the performance of the modulator, if some special feedback schematics are used.