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Dive into the research topics where Philippe Dupuy is active.

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Featured researches published by Philippe Dupuy.


Microelectronics Reliability | 2009

Characterization of ageing failures on power MOSFET devices by electron and ion microscopies

Donatien Martineau; Thomas Mazeaud; Marc Legros; Philippe Dupuy; Colette Levade; G. Vanderschaeve

Abstract Extreme electro-thermal fatigue tests have been performed to failure on power MOSFET devices that were later observed using electron and ion microcopy. At variance with devices from the former technology generation, fatigue-induced ageing of these components is observed only in the source metallization zone. An increase in drain–source resistance may originate from both a loss of contact between the wire bondings and the Al layer and/or an extensive decohesion between the metal grains. Failure modes include local melting of the Al and creation of eutectic alloys.


Microelectronics Reliability | 2007

Characterization and modelling of ageing failures on power MOSFET devices

Benjamin Khong; Marc Legros; Patrick Tounsi; Philippe Dupuy; X. Chauffleur; Colette Levade; G. Vanderschaeve; E. Scheid

A method based on the failure analysis of power MOSFET devices tested under extreme electrothermal fatigue is proposed. Failure modes are associated to several structural changes that have been investigated through acoustic, electron and ion microscopy. The main aging mode is related to the exponential increase in drain resistance due to delamination at the die attach. Earlier failures are observed when very local defects due to electrical over stresses (EOS) occur at the source metallization or at the wire bonding. Aging models were elaborated to account for the die attach delamination, but are still lacking to take in account the structural evolution of the Al metallization. This new methodology, based on accelerated tests and structural observations aims at designing a new generation of power components that will be more reliable.


Microelectronics Reliability | 2010

Characterization of alterations on power MOSFET devices under extreme electro-thermal fatigue

Donatien Martineau; Thomas Mazeaud; Marc Legros; Philippe Dupuy; Colette Levade

Extreme electro-thermal fatigue tests on power MOSFET-based switches for automotive applications have been performed in order to pinpoint their failure mechanisms. Contrary to devices from the former technology generation, the most important failure mode concentrates in the source metallization zone and consists in the degradation of the metallic layer. Intense intergranular and surface diffusion triggered by the thermal stresses between the Si substrate and the Al layer leads to intergranular crack formation. Around the ultimate life time (ULT) of the device, these intergranular cracks burrow almost down to the active transistor region and their density on the source surface is high enough to cause a loss of contact between the metal grains. The observed increase of the drain-source resistance could be attributed to this degradation that have qualitatively modeled. Observed melt down of the Al layer revealed by the formation of Al/Si eutectic could be the result of hot spots due to spikes in source resistance.


Microelectronics Reliability | 2005

Innovative Methodology for Predictive Reliability of Intelligent Power Devices Using Extreme Electro-thermal Fatigue

Benjamin Khong; Patrick Tounsi; Philippe Dupuy; X. Chauffleur; Marc Legros; A. Deram; Colette Levade; G. Vanderschaeve; Jean-Marie Dorkel; J. P. Fradin

In this paper, an innovative methodology for predictive reliability of intelligent power devices used in automotive applications is considered. Reliability management is done at all levels of the technological process. This method is based on the failure analysis along with electro-thermo- mechanical modeling and on extreme fatigue testing. A new power MOS device has been electrically fatigued in order to evaluate its failure modes. Using a thermally regulated test bench, electrical pulses were applied to the device until failure. This failure is associated to several structural changes that have been investigated through acoustic and electron microscopy. Delamination was observed preferentially at the solder between the copper heat sink and the die.


Microelectronics Reliability | 2014

Universal mechanisms of Al metallization ageing in power MOSFET devices

Donatien Martineau; Colette Levade; Marc Legros; Philippe Dupuy; Thomas Mazeaud

Power MOSFET devices are extensively used in the automotive industry, but their modes of ageing are still poorly understood. Here we focus on the physical degradation mechanisms that occur in the upper Al-based metallization layer (source). This layer undergoes thermo-mechanical structural modifications due to the combination of electrical pulses and differences between the various coefficients of thermal expansion. Using electronic and ionic microscopy, we show that ageing can be divided in 2 phases where dislocation-based plasticity and then grain boundary diffusion become predominant. As a result, grain boundary grooving and surface roughening follows a partial division of the later in disconnected Al grains. Such a degradation of the metallization has been widely observed in various devices. It may lead to the observed augmentation of resistivity and also to the focusing of the various current paths, promoting hot spots and subsequent failure.


Microelectronics Reliability | 2011

3D Electro-thermal modelling of bonding and metallization ageing effects for reliability improvement of power MOSFETs

Toufik Azoui; Patrick Tounsi; Philippe Dupuy; Laurent Guillot; Jean-Marie Dorkel

Abstract This paper presents a methodology, based on 3D electro-thermal simulation, to investigate failures of vertical power MOSFET due to metallization ageing of source terminal. Modelling steps to obtain a 3D finite element modelling of MOSFET are presented with the smart approximations and limitations of MOSFET electrical behaviour. The effects of bonding wire gauge and contact area with top metallization are studied to optimize the power device design. The power device thermal runaway phenomenon and hot spot formation has been simulated and discussed.


Microelectronics Reliability | 2013

Reliability of power MOSFET-based smart switches under normal and extreme conditions for 24 V battery system applications

Gilles Rostaing; Mounira Berkani; D. Mechouche; Denis Labrousse; Stéphane Lefebvre; Zoubir Khatir; Philippe Dupuy

This study aims to assess the reliability of smart converters for applications using 24 V batteries. It compares degradation effects and lifetime durations for similar dissipated energies when these smart power switches are subjected to normal and extreme protection test conditions. Three experimental ageing tests have been performed: (i) ageing tests under normal protection mode, (ii) ageing tests under repetitive inductive avalanche switching and (iii) ageing tests under repetitive short-circuit. Evolution of several electrical parameters such as on-state resistance; threshold voltage and saturation current have been monitored. Tested devices under normal condition and under repetitive inductive avalanche have failed after about the same number of cycles with the same dissipated energy. However, several results show a significant decrease of the lifetime under repetitive short-circuit tests for a similar dissipated energy.


Microelectronics Reliability | 2017

Mechanisms of power module source metal degradation during electro-thermal aging

Roberta Ruffilli; Mounira Berkani; Philippe Dupuy; Stéphane Lefebvre; Yann Weber; Marc Legros

The long-term reliability of power devices for applications in the automotive industry is limited by the electro-thermal and/or thermo-mechanical aging of the metallic parts. In the present work, we characterize the bonding wire and source metallization degradation of power MOSFETs-based devices under accelerated aging conditions, through electron and ion microscopy. The metal degradation is driven by an enhanced self-diffusion of aluminium (Al) atoms along the grain boundaries and a generalized fatigue crack propagation from the surface down to the silicon (Si) bulk. The metallization under the wire bonds is a critical location because it is initially plastically deformed during the bonding process. In addition, the wire-metal interface presents several imperfections, such as small cavities and Al oxide residues. During the electro-thermal cycles, they could be the starting point for harmful cracks that run along the interface (and eventually cause the wire lift-off or the cracking of the substrate). Whichever the propagation direction, the generation of these cracks locally increases the device resistance and temperature, and accelerates the aging process until failure. Mechanisms of power module source metal degradation during electro-thermal aging.


Microelectronics Reliability | 2015

In-depth investigation of metallization aging in power MOSFETs ☆

Roberta Ruffilli; Mounira Berkani; Philippe Dupuy; Stéphane Lefebvre; Yann Weber; Marc Legros

The long-term reliability of modern power MOSFETs is assessed through accelerated electro-thermal aging tests. Previous studies have shown that the source metallization (top metal and wires) is a failure-prone location of the component. To study how the top aluminum metallization microstructure ages, we have performed ion and electron microscopy and mapped the grain structure before and after avalanche and short-circuit aging tests. The situation under the bond wires is significantly different as the bonding process induces plastic deformation prior to aging. Ion microscopy seems to show two inverse tendencies: grain growth under the wires and grain refinement elsewhere in the metallization. Transmission electron microscopy shows that the situation is more complex. Rearrangement of the initial defect and grain structure happen below and away from the wire. The most harmful fatigue cracks propagate parallel to the wire/metal bonding interface.


Microelectronics Reliability | 2014

3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions

M. Riccio; Vincenzo d’Alessandro; Andrea Irace; Gilles Rostaing; Mounira Berkani; Stéphane Lefebvre; Philippe Dupuy

Abstract Active cycling of power devices operated in harsh conditions causes high power dissipation, resulting in critical electrothermal and thermo-mechanical effects that may lead to catastrophic failures. This paper analyzes the ageing-induced degradation of the chip metallization of a power MOSFET and its impact on the device robustness during short-circuit and unclamped inductive switching tests. A 3-D electrothermal simulator relying on a full circuit representation of the whole device is used to predict the influence of various ageing levels. It is found that ageing can jeopardize the robustness of the transistor when subject to short-circuit conditions due to the exacerbated de-biasing effect on the gate-source voltage distribution; conversely, this mechanism does not arise under unclamped inductive switching conditions. This allows explaining the difference in time-to-failure experimentally observed for the transistors subject to these tests and dissipating the same energy.

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Marc Legros

Centre national de la recherche scientifique

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Mounira Berkani

École Normale Supérieure

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Stéphane Lefebvre

Conservatoire national des arts et métiers

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Colette Levade

Centre national de la recherche scientifique

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G. Vanderschaeve

Centre national de la recherche scientifique

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Gilles Rostaing

École normale supérieure de Cachan

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Benjamin Khong

Centre national de la recherche scientifique

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