Philippe Hurat

Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs

An automated flow has been implemented to detect printability hotspots using a model-based solution, and to automatically fix these hotspots during final routing optimization. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. Since the semiconductor industry is currently limited to 193nm scanners, no relief is expected from the equipment side and must come from the design side. Rule-driven routers fail to capture hotspots, as they are based on ideal polygons that do not represent the real silicon image. Model-based hotspot detection can validate design manufacturability and will account for complex two-dimensional effects that stem from aggressive scaling of 193nm lithography. To enable this solution, manufacturing teams started to release model-based lithography checks; initially as a service using the manufacturing flow to check small cells, and now by releasing process information to designers for full-chip lithography hotspot detection. However, if manual fixing is manageable at the cell level, hotspot removal in large placed and routed blocks or even full chip is more challenging. Not only is full-chip litho/etch simulation required to have a reasonable runtime, but the fixing solution needs to be connectivity-aware and incremental with a very fine step size. This is required for a timing-aware solution that mitigates hotspots without adversely affecting timing closure. The automated flow links a hotspot detection solution and a chip routing optimization tool. The hotspot detection solution passes the hotspot locations and associated fixing guidelines to the chip routing optimization tool. The chip routing optimization tool removes the hotspots in an incremental fashion so as to have no significant impact on timing, but a significant impact on printability. This process of checking for hotspots and incrementally fixing them is iterated until a hotspot-free design is achieved. This paper describes how fabless designers have integrated this hotspot detection solution in their design flow and how the hotspot removal flow efficiently removed most hotspots in real designs, thereby providing DFM closure.

Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability

A methodology to predict the impact of systematic manufacturing variations on the parametric behavior of standard cells in an integrated circuit is described. Such a methodology can be applied to the analysis of a full chip composed of standard cell components, and reports layout context-dependent changes in chip timing and power. For lithography and etch-induced variability, a study of a 65nm standard cell library has been done to examine the influence of cell context when looking at cell delay and leakage at different focus and exposure conditions. Cell context, or proximity effects from neighboring cells, can have a significant impact on cell performance across a process window, especially through focus, which needs to be considered for silicon-aware circuit analysis. The traditional lookup table approach used in static timing analysis or leakage power analysis needs to be augmented with an instance-specific offset for each cell in a design. Contours need to be generated for each transistor in each cell at different process points and the corresponding delay and leakage offsets should be calculated based on these contours. Electrical characterization also enables the use of other context-specific process models, such as strain and dopant fluctuations, without altering the final output. This allows subsequent tools to use the information for circuit analysis. Such a methodology is thereby useful for process-aware static timing and power analysis.

Predictive models and CAD methodology for pattern dependent variability

Lithography, etch and stress are dominant effects impacting the functionality and performance of designs at 65 nm and below. This paper discusses pattern dependent variability caused by these effects and discusses a model-based approach to extracting this variability. A methodology to gauge the extent of this pattern dependent variability for standard cells is presented by looking at the difference in transistor parameters when the cell is analyze in different contexts. A full-chip methodology that addresses the delay change due to systematic varation has been introduced to analyze and repair a 65 nm digital design.

In-design process hotspot repair using pattern matching

As patterning for advanced processes becomes more challenging, designs must become more process-aware. The conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of runtime for designers, and also requires the release of highly confidential process information. Therefore, a more practical approach is required to make the In-Design process-aware methodology more affordable in terms of maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair (PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information. Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and released to check and fix subsequent designs. This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process hotspots in a design, specifically through the use of pattern matching and routing repair.

Layout induced variability and manufacturability checks in FinFETs process

With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies significant spatial intra-chip variability of transistor gate lengths which are systematic, as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper we describe such a chip timing methodology, its validation and implementation in microprocessor design. We also report results of layout optimization based on new pattern matching technology.

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

Convergent Automated Chip Level Lithography Checking and Fixing at 45nm

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

Implementation of silicon-validated variability analysis and optimization for standard cell libraries

Leveraging silicon validation, a model-based variability analysis has been implemented to detect sensitivity to systematic variations in standard cell libraries using a model-based solution, to reduce performance spread at the cell level and chip level. First, a simulation methodology to predict changes in circuit characteristics due to systematic lithography and etch effects is described and validated in silicon. This methodology relies on these two foundations: 1) A physical shape model predicts contours from drawn layout; 2) An electrical device model, which captures narrow width effects, accurately reproduces drive currents of transistors based on silicon contours. The electrical model, combined with accurate lithographic contour simulation, is used to account for systematic variations due to optical proximity effects and to update an existing circuit netlist to give accurate delay and leakage calculations. After a thorough validation, the contour-based simulation is used at the cell level to analyze and reduce the sensitivity of standard cells to their layout context. Using a random context generation, the contour-based simulation is applied to each cell of the library across multiple contexts and litho process conditions, identifying systematic shape variations due to proximity effects and process variations and determining their impact on cell delay. This methodology is used in the flow of cell library design to identify cells with high sensitivity to proximity effects and consequently, large variation in delay and leakage. The contour-based circuit netlist can also be used to perform accurate contour-based cell characterization and provide more silicon-accurate timing in the chip-design flow. A cell-variability index (CVI) can also be derived from the cell-level analysis to provide valuable information to chip-level design optimization tools to reduce overall variability and performance spread of integrated circuits at 65nm and below.

DFM reality in sub-nanometer IC design

The impact of sub-nanometer (below 90nm) effects on IC designs needs to be clearly understood to ensure that (1) manufacturing variations are considered during design to avoid catastrophic failures, and (2) the expected performance simulated in design is actually realized on silicon to avoid parametric failures. This paper discusses design for manufacturing solutions that enable designers to predict systematic manufacturing variations during design to detect and repair catastrophic and parametric failures. This paper presents real examples of design sensitivities to sub-nanometer manufacturing variations and the need to correctly analyze, optimize and verify the design before manufacturing by using appropriate EDA solutions which bring the effects of manufacturing variations in the design flow.

DFM for manufacturers and designers

At 90nm and 65nm, the semiconductor industry is condemned to use 193nm steppers and an overwhelming amount of resolution enhancement techniques (RET). Even when using the best RET solution available, some designs are more amenable to manufacturing than others and their initial yield or startup yield is higher. Design for manufacturing (DFM) has been a hotly discussed topic in both electronic design automation (EDA) and manufacturing communities, and to date much debate remains regarding its precise definition, let alone the solution. However, it is rather intuitive that, whatever the solution is, DFM needs to simultaneously satisfy several objectives in terms of optimizing yield, manufacturing cost and manufacturing friendliness; being transparent to the designer; protecting manufacturing intellectual property (IP); and having a sensible implementation. In this paper, we will describe a suitable technology that satisfies the data information sharing to ensure that both designers and manufacturers fulfill the expected initial and volume yield expectations. We describe how this technology may be applied pre- and post-tapeout to fulfill both designer and manufactures requirements.