Michel Luc Cote

Lithography-driven layout of logic cells for 65-nm node

The ITRS roadmap for the 65nm technology node, targets poly gate lengths of 65nm and poly pitches between 140-180nm. In addition, contact overlaps and spacing to diffusion contacts will need to be scaled down. It is very likely that the poly layer will be printed using 193nm high NA steppers and Strong Phase Shift Technologies. Attempts to capture the effect of RET on layout by adding more constraints to the desing rules make it difficult to lay out cells using manual tools and can also lead to sub optimal designs. In this paper we describe a methodology that couples automatic cell generation with Phase shifter insertion and image simulation to allow the design space to be explored more fully.

Layout printability optimization using a silicon simulation methodology

The manufacturing complexity at the 90 nm and 65 nm technology nodes severely impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trends behind this phenomenon. A new approach to layout that moves from an abstraction approach to a modeling approach is proposed. In this new methodology, layouts are processed using resolution enhancement techniques and the results are simulated using lithographical models for a specific manufacturing process. The simulation results are used to identify critical regions in the layouts. The layouts are then optimized based on this analysis to improve their printability, manufacturability and yield.

Standard cell printability grading and hot spot detection

Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moores law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.

New alternating phase-shifting mask conversion methodology using phase conflict resolution

A new methodology for completely phase-shifting a layout with creating local phase conflicts is proposed for lithographic techniques combining one phase-shifting mask and one binary mask exposure. Critical and non-critical areas of the layout are identified and phase conflicts are avoided by splitting the shifter regions from non-critical areas to non-critical areas without crossing critical areas. The out-of-phase splits of the shifter regions are removed using the binary exposure. Simulation results and experimental data collected for 90 nm technology node show no sign of process latitude loss around the areas where the shifters are split. The overlay latitude is commensurate with 90 nm technology scanner requirements (tool to itself). This approach can also be utilized at the cell library level by creating two copies of each cell with forced phase- shifting boundary conditions. The top and bottom of all the cells have the same phase while the left and right side of each cell have opposite phases, in degrees either 0 - 0 and 180 - 180 or 0 - 180 and 180 - 0. This implementation guarantees conflict-free cell creation and placement.

DFM for manufacturers and designers

At 90nm and 65nm, the semiconductor industry is condemned to use 193nm steppers and an overwhelming amount of resolution enhancement techniques (RET). Even when using the best RET solution available, some designs are more amenable to manufacturing than others and their initial yield or startup yield is higher. Design for manufacturing (DFM) has been a hotly discussed topic in both electronic design automation (EDA) and manufacturing communities, and to date much debate remains regarding its precise definition, let alone the solution. However, it is rather intuitive that, whatever the solution is, DFM needs to simultaneously satisfy several objectives in terms of optimizing yield, manufacturing cost and manufacturing friendliness; being transparent to the designer; protecting manufacturing intellectual property (IP); and having a sensible implementation. In this paper, we will describe a suitable technology that satisfies the data information sharing to ensure that both designers and manufacturers fulfill the expected initial and volume yield expectations. We describe how this technology may be applied pre- and post-tapeout to fulfill both designer and manufactures requirements.

Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing

Current cell-based design methodology is limited by the set of standard cells available in the library. Optimization is limited by the coarse granularity of drive strengths and lack of skewed drive strength in libraries. Including these variants would lead to a huge library set, which would very quickly become unmanageable. Moreover, gate-level timing data are more conservative than transistor level timing due to guard banding during cell characterization. Optimizing the cells in their context at the transistor level removes these limitations.

Fracture friendly optical proximity correction

Optical Proximity Correction (OPC) improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. Although the presence of these small shapes improves the final wafer image quality, it causes an increase in total figure count, longer fracture processing time, and the introduction of sliver figures. These undesirable artifacts can have a negative impact on the mask write time and mask image quality. In this paper we outline alternative OPC treatments which reduce the additional figures produced, and make the layout configurations friendlier to the subsequent mask fabrication phase. These include the alignment of neighboring small shapes during the OPC operation, and the preservation of jog alignment during the biasing phase. Illustrations of example pattern data, and improvement results in terms of figure counts are described.

Mask cost reduction and yield optimization using design intent

The relentless pursuit of Moores Law is pushing lithographical equipment to its limits. Extensive use of Resolution Enhancement Technologies (RET) during mask synthesis has allowed the industry to meet demand for density and performance at the 0.13um node and below. RET has been used to sustain the traditional model of printing edges as close as possible to the corresponding edges in the design layout. As technology moves to sub-100nm processes this model is proving to be both challenging and expensive to sustain. Pushing the RET tools to do an aggressive match between layout geometries and the printed pattern results in a large increase in mask cost. Even if this optimization is successful the resulting pattern may not provide the highest possible yield. In previous papers we demonstrated the use of design intent (DI) during mask synthesis to both reduce mask cost and improve yield. In this paper more results are described of how much improvement is possible on mask shot count and sliver count. We also investigate the cell level timing impact of our proposed methodology. Detailed timing results are presented and analyzed along with their impact on the design flow.

Hybrid AAPSM compliance methodology to ensure design for manufacturing

Dark field Alternating Aperture Phase Shift Mask (AAPSM) technology has developed into an enabling Resolution Enhancement Technology (RET) in the sub-100nm semiconductor device era. As phase shift masks are increasingly used to resolve features beyond just the most critical (for example transistor gates on the poly layer) the probability of phase conflicts (same phase across a feature) has increased tremendously. It has become imperative to introduce design practices that enable the semiconductor fabrication to take advantage of the improved performance that AAPSM delivers. In this paper we analyze the different causes for phase conflicts and the appropriate methods for detecting them, thus building the basis for the Hybrid AAPSM compliance flow. This approach leverages the strengths of existing DRC tools and the AAPSM conversion software. The approach is effective for minimizing the area penalty, thus very effective for density driven designs. By design, it is suited for custom or semi-custom layouts.

Optimizing manufacturability for the 65-nm process node

The 65nm technology node will require a more detailed assessment of the tradeoffs between performance, manufacturability and cost than any previous generation of technology. Circuits fabricated at the 65nm technology node need to use Strong Phase shifting techniques such as Full-Phase and Model based OPC in order to guarantee printability of critical layers, such as the poly layer. We presents a methodology whereby layouts are genrated base don a preliminary set of design rules for 65nm and the process latitude determined using image simulation software. Mask costs were also estiamted base donfigure counts of the required masks. Tradeoffs between mask costs, manufacturibility and density were made by small changes to the design rules. The simultaneous use of tools that integrate the design creation process with mask generation allows far better optimization than current methodology where physical design is separated from the downstream data preparation and processing.