Philippe Marquet

A Model-Driven Design Framework for Massively Parallel Embedded Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of these systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performance; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations. This article presents the Gaspard design framework for massively parallel embedded systems as a solution to the preceding issues. Gaspard uses the repetitive Model of Computation (MoC), which offers a powerful expression of the regular parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities, Gaspard allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high-level specifications of high-performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application.

Data-parallel load balancing stategies

Abstract Programming irregular and dynamic data-parallel algorithms must consider the effect of data distribution. The implementation of a load balancing algorithm is quite a difficult task for the programmer. However, a load balancing strategy may be developed independently of the application. The integration of such a strategy into the data-parallel algorithm may be relevant to a library or a data-parallel compiler run-time. We propose load distribution data-parallel algorithms for a class of irregular data-parallel algorithms called stack algorithms. Our algorithms allow the use of regular and/or irregular communication patterns to exchange the works between processors. The results of theoretical analysis of these algorithms are presented. They allow different load balancing algorithms to be compared and the identification of criteria to choose between them.

Model driven engineering for SoC co-design

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to SystemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

Towards UML 2 extensions for compact modeling of regular complex topologies

The MARTE RFP (Modeling and Analysis of Real-Time and Embedded systems) was issued by the OMG in February 2005. This request for proposals solicits submissions for a UML profile that adds capabilities for modeling Real Time and Embedded Systems (RTES), and for analyzing schedulability and performance properties of UML specifications. One of the particular request of this RFP concerns the definition of common high-level modeling constructs for factorizing repetitive structures, for software, hardware and allocation modeling of RTES. We propose an answer to this particular requirement, based on the introduction of multi-dimensional multiplicities and mechanisms for the description of regular connection patterns between model elements. This proposition is domain independent. We illustrate the use of these mechanisms in an intensive computation embedded system co-design methodology. We focus on what these factorization mechanisms can bring for each of the aspects of the co-design: application, hardware architecture, and allocation.

GASPARD: a visual parallel programming environment

In this paper, we present GASPARD (Graphical Array Specification for Parallel and Distributed computing), our visual programming environment devoted to the development of parallel applications. Task and data parallelism paradigms of parallel computing are mixed in GASPARD to achieve a simple programming interface. We use the printed circuit metaphor. The programmer specifies tasks and instantiates by plugging them into a slot (task parallelism). Data parallelism is achieved by specifying the data the task uses. By mixing textual and visual programming, we achieve a convenient interface useful for scientific programming. The interface is also well suited for meta-computing deployment. This kind of programming is very useful for numerical simulation.

Scalable mpNoC for massively parallel systems - Design and implementation on FPGA

The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device. These parallel systems require a cost-effective yet high-performance interconnection scheme to provide the needed communications between processors. The massively parallel Network on Chip (mpNoC) was proposed to address the demand for parallel irregular communications for massively parallel processing System on Chip (mppSoC). Targeting FPGA-based design, an efficient mpNoC low level RTL implementation is proposed taking into account design constraints. The proposed network is designed as an FPGA based Intellectual Property (IP) able to be configured in different communication modes. It can communicate between processors and also perform parallel I/O data transfer which is clearly a key issue in an SIMD system. The mpNoC RTL implementation presents good performances in terms of area, throughput and power consumption which are important metrics targeting an on chip implementation. mpNoC is a flexible architecture that is suitable for use in FPGA-based parallel systems. This paper introduces the basic mppSoC architecture. It mainly focuses on the mpNoC flexible IP based design and its implementation on FPGA. The integration of mpNoC in mppSoC is also described. Implementation results on a Stratix II FPGA device are given for three data-parallel applications ran on mppSoC. The obtained good performances justify the effectiveness of the proposed parallel network. It is shown that the mpNoC is a lightweight parallel network making it suitable for both small as well as large FPGA-based parallel systems.

FPGA-based many-core System-on-Chip design

Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architectures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Programmable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architectures with current design methodologies based on recent integration technologies. Flexibility offered by these new design tools allows design space exploration to search for the most effective implementations. This work introduces an IP-based design methodology for easy building configurable and flexible massively parallel SIMD processing on FPGA platforms. The proposed approach allows implementing a generic parallel architecture based on IP assembly that can be tailored in order to better satisfy the requirements of highly-demanding applications. The experimental results show effectiveness of the design methodology as well as the performances of the implemented SoC.

Compilation Principle of a Specification Language Dedicated to Signal Processing

ARRAY-OL, developed by Thomson Marconi Sonar, is a programming language dedicated to signal processing. An ARRAY-OL program specifies the dependencies between array elements produced and consumed by tasks. In particular, temporal dependencies may be specified by referencing elements that belong to an infinite dimension of an array. A basic compilation strategy of ARRAY-OL on a workstation has been defined. This basic compilation does not allow the generation of efficient code for any ARRAY-OL application; specifically those defining infinite arrays. We propose to transform such applications to hierarchical ARRAY-OL applications that may be compiled with ARRAY-OL basic strategy. We introduce a formal representation of ARRAY-OL applications, which is a relation between points of Zn spaces; code transformations are applied at this level. In this paper we show how the transformation process is used during the compilation phase of a representative application.

Visual data-parallel programming for signal processing applications

Matrix manipulation programs are easily developed using a visual language. For signal processing, a graph of tasks operates on arrays. Each task iterates the same code on different patterns tilling these arrays. In this case visual specifications of dependencies between the pattern elements are enough to define an application. From the ARRAY-OL language developed by Thomson Marconi Sonar, we propose a graphical environment, GASPARD, dedicated to the data-parallel paradigm. Only elementary SPMD tasks are textual. A full environment has been implemented; it includes a graphical editor, a code transformer and a code generator for SMP computers.

Asymmetric scheduling and load balancing for real-time on linux SMP

The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarantee the preemption of a processor when the system has to schedule a real-time task. The basic idea of ARTiS is to assign a selected set of processors to real-time operations. A migration mechanism of non-preemptible tasks insures a latency level on these real-time processors. Furthermore, specific load-balancing strategies allows ARTiS to benefit from the full power of the SMP systems: the real-time reservation, while guaranteed, is not exclusive and does not imply a waste of resources. ARTiS have been implemented as a modification of the Linux scheduler. This paper details the evaluation of the performance we conduct on this implementation. The level of observed latency shows significant improvements when compared to the standard Linux scheduler.