Pierre Boulet

(Pen)-ultimate tiling?

In the framework of perfect loop nests with uniform dependences, tiling is a technique used to group elemental computation points so as to increase computation granularity and to reduce the overhead due to communication time. We review existing approaches from the literature, together with the optimization criteria that are used for determining a “good” or “optimal” tiling. Then we explain the need to introduce yet another criterion for defining “optimal tiling” in a scalable environment. Althoug hour criterion is more complex than previously used ones, we are able to prove a theorem on optimality, and to provide a constructive method for defining the “optimal tiling”.

Loop parallelization algorithms: from parallelism extraction to code generation

Abstract In this paper, we survey loop parallelization algorithms, analyzing the dependence representations they use, the loop transformations they generate, the code generation schemes they require, and their ability to incorporate various optimizing criteria such as maximal parallelism detection, permutable loop detection, minimization of synchronizations, easiness of code generation, etc. We complete the discussion by presenting new results related to code generation and loop fusion for a particular class of multidimensional schedules called shifted linear schedules. We demonstrate that algorithms based on such schedules lead to simple codes.

Algorithmic issues on heterogeneous computing platforms

This paper discusses algorithmic issues when computing with a heterogeneous network of work-stations (the typical poor mans parallel computer). Dealing with processors of different speeds requires to use more involved strategies than block-cyclic data distributions. Dynamic data distribution is a first possibility but may prove impractical and not scalable due to communication and control overhead. Static data distributions tuned to balance execution times constitute another possibility but may prove ineffcient due to variations in the processor speeds (e.g. because of different workloads during the computation). We introduce a static distribution strategy that can be refined on the fly, and we show that it is well-suited to parallelizing scientific computing applications such as finite-difference stencils or LU decomposition.

Mode-automata based methodology for scade

In this paper, we present a new design methodology for synchronous reactive systems, based on a clear separation between control and data flow parts. This methodology allows to facilitate the specification of different kinds of systems and to have a better readability. It also permits to separate the study of the different parts by using the most appropriate existing tools for each of them. Following this idea, we are particularly interested in the notion of running modes and in the Scade tool. Scade is a graphical development environment coupling data processing and state machines (modeled by the synchronous languages Lustre and Esterel). It can be used to specify, simulate, verify and generate C code. However, this tool does not follow any design methodology, which often makes difficult the understanding and the re-use of existing applications. We will show that it is also difficult to separate control and data flow parts using Scade. Regulation systems are better specified using mode-automata which allow adding an automaton structure to data flow specifications written in Lustre. When we observe the mode-structure of the mode-automaton, we clearly see where the modes differ and the conditions for changing modes. This makes it possible to better understand the behavior of the system. In this work, we try to combine the advantages of Scade and running modes, in order to develop a new design methodology which facilitates the study of several systems by respecting the separation between control and data flows. This schema is illustrated through the Climate case study suggested by Esterel Technologies, in order to exhibit the benefits of our approch compared to the one advocated in Scade.

Static tiling for heterogeneous computing platforms

In the framework of fully permutable loops, tiling has been extensively studied as a sourceto-source program transformation. However, little work has been devoted to the mapping and scheduling of the tiles on physical processors. Moreover, targeting heterogeneous computing platforms has to the best of our knowledge, never been considered. In this paper we extend static tiling techniques to the context of limited computational resources with diAerent-speed processors. In particular, we present eAcient scheduling and mapping strategies that are asymptotically optimal. The practical usefulness of these strategies is fully demonstrated by MPI experiments on a heterogeneous network of workstations. ” 1999 Elsevier Science B.V. All rights reserved.

Projection of the Array-OL specification language onto the Kahn process network computation model

The Array-OL specification model has been introduced to model systematic signal processing applications. This model is multidimensional and allows to express the full potential parallelism of an application: both task and data parallelism. The Array-OL language is an expression of data dependences and thus allows many execution orders. In order to execute Array-OL applications on distributed architectures, we show here how to project such specification onto the Kahn process network model of computation. We show how Array-OL code transformations allow to choose a projection adapted to the target architecture.

Scanning polyhedra without Do-loops

We study in this paper the problem of polyhedron scanning which appears for example when generating code for transformed loop nests in automatic parallelization. After a review of related works, we detail our method to scan affine images of polyhedra. After some experimental results we show how our method applies to unions of affine images of polyhedra. We have taken the option to generate low level code without loops. This has allowed us to have a completely general and fully parameterized method without losing efficiency.

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives

Embedded systems have become an essential aspect of our professional and personal lives. From avionics, transport and telecommunication systems to general commercial appliances such as smart phones, high definition TVs and gaming consoles; it is difficult to find a domain where these systems have not made their mark. Moreover, Systems-on-Chips (SoCs) which are considered as an integral solution for designing embedded systems, offer advantages such as run-time reconfiguration that can change system configurations during execution, depending upon Quality-of-Service (QoS) criteria such as performance and energy levels. This article deals with aspects related to modeling of these configurations, useful for describing various states of an embedded system, from both structural and operational viewpoints. Our proposal adapts a high abstraction level approach based on the principles of Model-Driven Engineering (MDE) and takes into account the UML MARTE profile for modeling of real-time and embedded systems. Elevating the design abstraction levels help to increase design productivity and achieve execution platform independence, among other advantages. The article details the current proposition of configurations in MARTE via some examples, and points out the advantages as well as some limitations, mainly concerning the semantic aspects of the defined concepts. Finally, we report our experiences on the modeling of an alternate notion of configurations and execution modes within the MARTE compliant Gaspard2 SoC Co-Design framework that has been successful for the design as well as implementation of FPGA based SoCs.

Model driven engineering for SoC co-design

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to SystemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing

Intensive signal processing applications appear in many application domains such as video processing or detection systems. These applications handle multidimensional data structures (mainly arrays) to deal with the various dimensions of the data (space, time, frequency). A specification language allowing the direct manipulation of these different dimensions with a high level of abstraction is a key to handling the complexity of these applications and to benefit from their massive potential parallelism. The Array-OL specification language is designed to do just that. We introduce here an extension of Array-OL to deal with states or delays by the way of uniform inter-repetition dependences. We show that this specification language is able to express the main patterns of computation of the intensive signal processing domain.