Philippe Millet

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

Reconfigurable architectures and NoC (Network-on- Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price < 10% in area in power consumption with respect to the overall system.

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform

The FlexTiles Platform has been developed within a Seventh Framework Programme project which is co-funded by the European Union with ten participants of five countries. It aims to create a self-adaptive heterogeneous many-core architecture which is able to dynamically manage load balancing, power consumption and faulty modules. Its focus is to make the architecture efficient and to keep programming effort low. Therefore, the concept contains a dedicated automated tool-flow for creating both the hardware and the software, a simulation platform that can execute the same binaries as the FPGA prototype and a virtualization layer to manage the final heterogeneous many-core architecture for run-time adaptability. With this approach software development productivity can be increased and thus, the time-to-market and development costs can be decreased. In this paper we present the FlexTiles Development Platform with a many-core architecture demonstration. The steps to implement, validate and integrate two use-cases are discussed.

TULIPP: Towards ubiquitous low-power image processing platforms

Many industrial domains rely on vision-based applications which require to comply with severe performance and embedded requirements. Tulipp will develop a reference platform which consists of a hardware system, a tool chain and a real-time operating system. This platform defines implementation rules and interfaces to tackle power consumption issues while delivering high, energy efficient and guaranteed computing performance for image processing applications. Using this reference platform will enable designers to develop a complete solution at a reduced cost to meet the typical embedded systems requirements: Size, Weight and Power. Moreover, for less constrained systems which performance requirements cannot be fulfilled by one instance of the platform, the reference platform will also be scalable so that the resulting boards can be chained for higher processing power. The instance of the reference platform developed during the project will be use-case driven and split between the implementation of: a reference hardware architecture — a scalable low-power board; a low-power operating system and image processing libraries; a productivity-enhancing tool chain. It will lead to three proof-of-concept demonstrators across different application domains: real-time and low-power medical image processing product prototype of surgical X-ray system (mobile c-arm); embedded image processing systems within Unmanned Aerial Vehicles (UAVs); automotive real time embedded systems for driver assistance. Tulipp will set up an ecosystem and will closely work with standardization organizations to propose new standards derived from its reference platform to the industry.

FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture

This paper introduces the FlexTiles platform, which consist of a manycore architecture associated with a complete tool flow. The different components of the manycore architecture are based on general purpose processors (GPP), low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. Thus, in order to mask the underlying heterogeneity of such an architecture, innovative software mechanism and hardware interface were defined. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. In order to facilitate the architecture adaptation under different scenarios, a programming model that considers both static and dynamic behaviors is proposed. The proposed architecture has been implemented on a FPGA platform and has shown the validity of the proposed solution.

FlexTiles: self adaptive heterogeneous manycore based on flexible tiles (FP7 project)

We present the FP7 project FlexTiles which main objective is to develop a heterogeneous manycore with self adaptive capabilities.

Developing Low-Power Image Processing Applications with the TULIPP Reference Platform Instance

Today, many industrial domains rely on vision-based embedded systems. High computing performance of the embedded platform is a mandatory feature for modern image processing applications. Yet, these embedded systems have to comply with strict requirements regarding size, weight and energy efficiency. Tulipp will develop a reference platform, which defines implementation rules and interfaces to tackle power consumption issues while delivering high, energy-efficient and guaranteed computing performance. This allows developers to find the optimal solution for their image processing application, to comply with the requirements of their embedded system and to reduce the time spent on the development and iteration process. The Tulipp reference platform consists of a hardware system, supportive development utilities and a real-time operating system (RTOS) . Chained platforms provide scalability and higher processing power. The project develops and provides: a reference hardware architecture—a scalable low-power board; a low-power operating system and image processing libraries; a productivity-enhancing toolchain. In addition, Tulipp will publish a reference platform handbook, which will help developers building and using their custom instance of the reference platform. The project is use case driven, providing real-time low-power demonstrators of a medical image processing application, automotive embedded systems for driver assistance (ADAS) and applications for Unmanned Aerial Vehicles (UAVs). The close connection to its set-up ecosystem and standardization organizations will allow the Tulipp project to propose new standards derived from its reference platform and handbook to the industry.

Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera: Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera

This paper describes a methodology to improve the energy efficiency of high-performance mul-tiprocessor architectures with Dynamic and Partial Reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. FPGAs are increasingly being used in cameras owing to their suitability for real-time image processing with intensive, high-performance tasks, and to the recent advances in dynamic reconfiguration that further improve energy efficiency. The approach used to best exploit DPR is based on the better coupling of two decisive elements in the problem of heterogeneous deployment: design space exploration and advanced scheduling. We show how a tight integration of exploration, energy-aware scheduling , common power models, and decision support in heterogeneous DPR multiprocessor SoC mapping can be used to improve the energy efficiency of hardware acceleration. Applying this to a mobile vehicle license plate tracking and recognition service results in up to a 19-fold improvement in energy efficiency compared with software multiprocessor execution (in terms of energy–delay product), and up to more than a 3-fold improvement compared with a multipro-cessor with static hardware acceleration (i.e. without DPR).

Recent advances in joint optical-digital design for optronics applications

Increasing the capture volume of visible cameras while maintaining high image resolutions, low power consumption and standard video-frame rate operation is of utmost importance for hand-free night vision goggles or embedded surveillance systems. Since such imaging systems require to operate at high aperture, their optical design has become more complex and critical. Therefore new design alternatives have to be considered. Among them, wavefront coding changes and desensitizes the modulation transfer function (MTF) of the lens by inserting a phase mask in the vicinity of the aperture stop. This smart filter is combined with an efficient image processing that ensures optimal image quality over a larger depth of field. In this paper recent advances are discussed concerning design and integration of a compact imaging system based on wavefront coding. We address the design, the integration and the characterization of a High Definition (HD) camera of large aperture (F/1.2) operating in the visible and near infrared spectral ranges, endowed with wavefront coding. Two types of phase masks (pyramidal and polynomial) have been jointly optimized with their deconvolution algorithm in order to meet the best performance along an increased range of focus distances and manufactured. Real time deconvolution processing is implemented on a Field Programmable Gate Array. It is shown that despite the high data throughput of an HD imaging chain, the level of power consumption is far below the initial specifications. We have characterized the performances with and without wavefront coding through MTF measurements and image quality assessments. A depth-of- field increase up to x2.5 has been demonstrated in accordance with the theoretical predictions.