Phillip Christie

A differential equation for placement analysis

A first-order differential equation for placement analysis is derived by considering the competing processes that generate and terminate wires crossing a circuit partition. The solution of this equation provides an estimate for the number of wires needed by a circuit partition for external communication and corresponds to the information normally associated with Rents rule. The rate model is shown to account not only for the simple power-law form of Rents rule for small partition sizes but also for deviations from power-law behavior observed for larger partition sizes. The accuracy of the model is validated by comparing solutions of the differential equation with experimental data extracted from a variety of netlists. The netlists, ranging from 10000 to 68000 cells, were optimized using a commercial placement tool. The accurate modeling of terminal-cell data results in a more robust predictive model for the distribution of wire lengths. This improved model accurately captures the change in the distribution of wires as the level of circuit placement optimization ranges from random to highly optimized placement. In addition, the new model provides an explanation for the experimentally observed inflection point and local maximum in the wire length distribution of some netlists.

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.

Multi-objective optimization of interconnect geometry

The rapid increase in the number of wiring layers due to improved planarization and metallization techniques permits spatial resources to be traded for improved performance. Yield, power dissipation and propagation delay are all sensitive to the selection of the pitch and width of wires in each layer. As in many other engineering design problems, however, there exists no unique solution which simultaneously optimizes all aspects of system performance. The best that can be achieved is the identification of the optimal surface within the multi-objective performance space. A single design can be chosen from this list a posteriori using additional selection criteria which may depend, for example, on the specific details of the product application. This paper investigates the use of Pareto genetic algorithms to explore the extent of multi-objective optimal surfaces. The tradeoffs between yield, power-dissipation and cycle time for a benchmark netlist are examined as a function of in-plane geometry for a seven-layer interconnect.

Rent exponent prediction methods

A wide variety of models for estimating the distribution of on-chip net lengths assume an accurate estimate for an empirical parameter called the Rent exponent. Due to its definition as an exponent, these models are sensitive to its precise value, and careful selection is essential for good estimates of layout requirements and cycle times. In addition, it is also important to be able to predict changes in the Rent exponent with (possibly discontinuous) changes in interconnect technology. This paper presents a range of methods for estimating the Rent exponents of arbitrarily large gate placements as a function of optimization procedure and the level of fan-out present in the netlist. The first part of the paper describes a rapid algorithmic approach which combines the self-similar, or fractal attributes of small wiring cells with a Monte Carlo sampling method. This method is shown to accurately account for variations in both the wiring signature of the netlist and for the effects of most algorithms used for placement optimization. The second part of the paper presents an analytical model for Rent exponent prediction, based on a renormalization group transformation. This transformation is designed to filter out information which does not contribute to the scale-invariant properties of the optimized netlist enabling the derivation of a closed-form expression for the Rent exponent.

Stochastic wire length sampling for cycle time estimation

Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large to allow average wire lengths to be used. This paper investigates the accuracy of this mean value assumption by comparing cycle times calculating using average wire lengths with cycle times calculated using wires sampled from an estimate of the wire length distribution in each wiring layer. The sampling algorithm provides a more accurate calculation of the cycle time and also an estimate of its variation due to the inherently stochastic nature of the layout process. Results for a benchmark netlist, implemented in 0.25 μm technology, indicate that for a logic depth of 25 the mean value assumption is satisfactory and that clock rate has a standard deviation of approximately 5% of this mean value due to the inherently stochastic nature of the layout process.

Design And Simulation Of Optically Interconnected Computer Systems

Optical interconnections within mainframe computers were first proposed over ten years ago, but the debate continues on their effectiveness at a given interconnection level (board-to-board, chip-to-chip, etc.) In order to gauge the impact of this new technology several studies have discussed the power and speed limitations of electrical interconnections. Unfortunately, hard data is difficult to generate due to the immense complexity of the systems involved. Many of these problems are due to the conceptual view of a computer as an array of devices connected by wires. As we move into the interconnect-limited regime it becomes advantageous to consider the system as a pattern of wires that must be excited by devices. It is in this spirit that we propose a model of the computer which is based on the statistical analysis of its interconnections. Previous work in this area has quoted the performance of interconnections in terms of effective averages. In this paper we produce closed-form analytic expressions for the interconnection distribution as a function of hierarchy. A self-similar hierarchical model, satisfying the observed power-law relationship between circuit complexity and interconnection count, is used to mimic the interconnection distribution within large computer systems. The length distribution function is accessible at all hierarchical levels. This enables the operational performance of optical interconnection strategies to be monitored and compared with their electrical counterparts.

A canonical ensemble analysis of interconnect-limited systems

The author presents a new analysis of the maximum entropy model used for calculating the statistical properties of computer systems optimized using the simulated annealing algorithm. Here a canonical ensemble of equivalent systems is introduced, which naturally relates the annealing temperature of the software to the effective temperature of the system being annealed. It is proposed that a modified canonical ensemble may be appropriate for the design of optimized neural network architectures. A power-law ensemble is proposed which will incorporate both wire length optimization and geometrical constraints into a single unified model of computer construction.<<ETX>>

CLOUDS, COMPUTERS AND COMPLEXITY

Modern computers are complex. But is it meaningful to say that a computer is complex when compared to a system as intricate as the brain? Is a miniature version of a computer more complex, more intricate—or just smaller? How can we begin to conceive of ever more complex systems if we lack the ability to describe them? Clearly, we need to add new terminology to our descriptive lexicon of complexity.

Wire layer geometry optimization using stochastic wire sampling

The variation of in-plane interconnect geometry (pitch and width) as a function of wiring level results in improved system level performance because the properties of each wiring layer may be tailored to the characteristic lengths of the wires allocated to it. Performance metrics such as interconnect functional yield, and power dissipation are well suited to layer-by-layer optimization since they are determined by geometrical properties integrated across the wiring layer. The cycle time of a circuit, on the other hand, is a poor candidate for geometry optimization because it may be determined by a single wire length allocated to a single wiring layer. This paper addresses this issue by combining a genetic algorithm for geometry optimization with stochastic sampling of the wires lengths used in determining the signal delay within a key circuit block. We present results on how the stability of the optimal cycle time geometries vary as a function of the stochastic variations inherent in the layout process.

Theoretical and experimental analysis of wire segment holograms for statistical interconnect metrology

Theoretical and experimental results using computer generated wire segment holograms for statistical interconnect metrology are presented. Test structures have been constructed using a process capable of imaging 1-/spl mu/m features and consist of arrays of wire segments illuminated by a He-Ne Laser. Since the holograms are fabricated at the same time as actual wires on the wafer, the quality of the projected image correlates with the emergence of global feature patterning errors. Specifically, this paper presents data on the effect of varied exposure time on the intensity of the projected image. An initial statistical analysis indicates that the test structures are capable of detecting variations in wire geometry which are approximately 1.0% of the nominal wire width. It is anticipated that significant improvements to this level of sensitivity can be obtained by optimization of the holographic encoding process and test image selection.