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Featured researches published by Phuc C. Pham.


bipolar circuits and technology meeting | 1990

A low power differential bus utilizing novel split level bus technique

Ray D. Sundstrom; Phuc C. Pham; Dwight D. Esgar; Cleon Petty

A low-power differential bus utilizing a novel split level bus (SLB) technique is described. There are several inherent advantages with the SLB. The bus operates at full differential mode at all times so the receiver never detects an indeterminate state. There are no reference levels on the bus, allowing full common mode range. Making D and DB both passive or active at the same time can make the SLB appear similar to single-ended operation. This makes any present single-ended bus technique, such as future-bus arbitration, directly applicable to the SLB. The reduced power dissipated by the internal circuitry, and reduction in power supply pins, allow wider parts in the same package. The losses on the bus are reduced and the bus power remains constant for any number of drivers.<<ETX>>


bipolar/bicmos circuits and technology meeting | 1995

The architecture, logic, and circuit design of a bipolar, 200 Mbyte/sec, serializing data mover IC, with 32-bit TTL-compatible parallel I/O and unique 1.8 Gbit/sec 'cutoff driver' differential PECL serial I/O

Phil Jeffery; David K Ford; Phuc C. Pham; Michael D. Reed; Naridini Srinivasan; Bernie Weir

This paper discusses the architecture, logic design, and circuit design of the Autobahn Spanceiver-a serializing transceiver IC that facilitates movement of arbitrarily large blocks of 32-bit parallel TTL data at data rates up to 200 MBytes/sec, between two or more nodes on a shared, controlled-impedance, half-duplex, 1.8 Gbit/sec, differential-PECL serial channel.


bipolar circuits and technology meeting | 1989

A low power bipolar ECL standard cell library utilizing a novel design methodology and complementary bipolar driver

Phuc C. Pham; E. Kawamoto; Greg Davis; Lou Spangler

A low-power bipolar ECL (emitter-coupled-logic) standard cell library built with a design methodology which simplifies the layout of primitive cells by utilizing a subprimitive cell layout as a building block is discussed. The library utilizes complementary bipolar (CBIP) drivers for high drive capability without an accompanying increase in power dissipation. The method provides maximum flexibility in driver selection while minimizing cell library overhead. Analysis of the performance of the CBIP drivers using MSPICE simulations show superior drive capability over emitter follower drivers for load capacitances greater than 0.2 pF.<<ETX>>


Archive | 1996

Method for synchronizing signals and structures therefor

David K Ford; Philip A. Jeffery; Phuc C. Pham


Archive | 1994

Monolithic shielded integrated circuit

Phuc C. Pham; Charles B. Siragusa; John C. Veto


Archive | 1991

On-chip self-test circuit

Phuc C. Pham; Paul B Sofianos


Archive | 1991

Voltage controlled oscillator employing negative resistance

Phuc C. Pham; Carl Denig


Archive | 1993

Voltage controlled oscillator having cascoded output

Phuc C. Pham


Archive | 1993

Temperature compensated voltage regulator having beta compensation

Phuc C. Pham; Lou Spangler; Greg Davis


Archive | 1992

Voltage controlled oscilator having controlled bias voltage, AGC and output amplifier

Phuc C. Pham; Gregory A. Davis; Harold L. Spangler

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