Pidugu L. Narayana

State machine design for generating empty and full flags in an asynchronous FIFO

Full and empty flag generator for synchronous FIFOS

Oscillator circuit controlled by programmable logic

Method, architecture and circuit for controlling and/or operating an oscillator

Signal generation decoder circuit and method

Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness

State machine design for generating half-full and half-empty flags in an asynchronous FIFO

Composite flag generation for DDR FIFOs

Programmable read-write word line equality signal generation for FIFOs

Distributed test architecture for multiport RAMs or other circuitry