Andrew L. Hawkins

Single ended simpler dual port memory cell

Testing method for FIFOS

Single ended dual port memory cell

State machine design for generating empty and full flags in an asynchronous FIFO

Full and empty flag generator for synchronous FIFOS

Address counter test mode for memory device

Signal generation decoder circuit and method

Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness

State machine design for generating half-full and half-empty flags in an asynchronous FIFO

Read bitline writer for fallthru in FIFO's