Pier Luca Montessoro

MOZART: a concurrent multilevel simulator

MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZARTs syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past. >

Creator: General and efficient multilevel concurrent fault simulation

Accuracy, generality and efficiency are critical factors when fault simulation of VLSI circuits is the target. The concurrent algorithm is the only approach that satisfies these requirements. In the paper the minimal information concept is discussed, and its applications on the key algorithms for concurrent event-driven simulation are shown. New advanced generalized techniques are presented for the first time in a truly unified context. They are not related to a specific abstraction level, and lead to an intrinsic multilevel concurrent simulation algorithm. The implementation in the fault simulator Creator is described.

Creator: new advanced concepts in concurrent simulation

Creator is a concurrent simulator for design verification and fault simulation of large circuits that highly integrates several traditional and innovative techniques. This is achieved by the introduction of a minimal information concept. Traditional techniques derived from previous works are Multiple List Traversal (MLT), trigger inhibition, fraternal event processing, list events, acid clock suppression, whereas the new ideas are function lists and evaluation functions, persistence time, positioning algorithm, evaluation triggering algorithm, combination of Single List Traversal (SLT) and MLT, and the implementation of transport delay in fault simulation. Generally the concurrent algorithm increases in complexity and the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. To overcome this limitation, all the Creators techniques are not related to a specific abstraction level and lead to an intrinsic multilevel concurrent fault simulator. Experimental results are reported to compare Creator with our previous simulator and the state-of-the-art commercial simulator Verifault-XL on several platforms. >

General and efficient multiple list traversal for concurrent fault simulation

Accuracy, generality and efficiency are critical factors when fault simulation of VLSI circuits is the target. The concurrent algorithm is the only solution when generality and accuracy is required. Its differential representation of the network status saves memory and CPU time, but due to its complexity the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. In the paper the minimal information concept is discussed, and its applications to the key algorithms for concurrent event-driven simulation are shown. New advanced generalized techniques for multiple list traversal (MLT), trigger inhibition, fraternal event processing, list events, edge sensitive inputs, compile-driven evaluation functions, functional fault sources and clock suppression are presented for the first time in a truly unified context.<<ETX>>

The performance of the concurrent fault simulation algorithms in MOZART

MOZART is a concurrent fault simulator for large circuits described in the RT, functional gate, and switch levels. Performance is gained by means of techniques aimed at the reduction of unnecessary activity. Two such techniques are levelized two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active faulty machines can dramatically improve fault simulator performance. These and related issues are discussed, and analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A novel performance metric is introduced for fault simulation that is based on comparison with the serial algorithm and is more accurate than those currently used.<<ETX>>

The fault dropping problem in concurrent event-driven simulation

The dynamic removal of faults before the end of the test pattern is reached, called fault dropping (FD), is considered. The conventional technique, called synchronous FD, is analyzed. An asynchronous FD method is introduced and its performance compared with that of the conventional method. It is based on the concept of removing descriptors while the simulation procedures access the data structure. This technique guarantees the maximum efficiency in reducing the computational effort. Experimental results show that it can considerably speed up simulation, particularly for large networks. It is shown that a mixed synchronous/asynchronous approach can optimize the total amount of memory needed. >

The comparative and concurrent simulation of discrete-event experiments

Discrete-Event Simulation is a powerful, but underexploited alternative for many kinds of physical experimentation. It permits what is physically impossible or unaffordable, to conduct and run related experiments in parallel, against each other. Comparative and Concurrent Simulation (CCS) is a parallel experimentation method that adds a comparative dimension to discrete-event simulation. As a methodology or style, CCS resembles a many-pronged rake; its effectiveness is proportional to the number of prongs—the number of parallel experiments. It yields information in parallel and in time order, rather than in the arbitrary order of one-pronged serial simulations. CCS takes advantage of the similarities between parallel experiments via the one-for-many simulation of their identical parts; if many experiments are simulated, then it is normally hundreds to thousands times faster than serial simulation. While CCS is a one-dimensional method, a more general, multi-dimensional or multidomain version is MDCCS. MDCCS permits parent experiments to interact and produce offspring experiments, i.e., to produce more, but smaller experiments, and many zero-size/zero-cost experiments. MDCCS is more general, informative, and faster (usually over 100:1) than CCS for most applications. It handles more complex applications and experiments, such as multiple faults, variant executions of a software program, animation, and others.

Fault simulation in a multilevel environment: the MOZART approach

MOZART is a concurrent fault simulator for large circuits described at the RT, functional, gate, and switch levels. Performance is gained by means of techniques aimed at the reduction of unnecessary activity. Two such techniques are levelized two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation that is based on comparison with the serial algorithm and is more accurate than those used up till now. Possible tradeoffs between the speeds of fault-free and fault simulations are discussed.<<ETX>>

System verification using multilevel concurrent simulation

The verification of multilevel designs in a single simulator environment can be achieved efficiently using concurrent simulation. MCS is a research simulation tool developed in conjunction with Compaq Computer Corporation and Draper Laboratories. MCS overcomes limitations imposed by merged simulator approaches. MCS achieves this by incorporating techniques that are not specific to any abstraction level, making it attractive for testing interface interconnects and mixed-mode logic. We describe our approach, which is a cohesive simulator platform based on concurrent simulation algorithms.

Multi-level concurrent simulation

As the size and complexity of logic designs become increasingly large, computing resources to verify the correctness of systems on a chip and develop quality test patterns for manufacturing are becoming strained. Using behavioral models in simulation captures the functional characteristics of a design block without necessarily relying on a specific implementation. Models can be interchanged or replaced by abstracted models as more detailed models become available or as more high level system testing is required. This will allow larger systems to be simulated as a cohesive unit. In addition, by utilizing function lists to dynamically create faulty behaviors, we will demonstrate its versatility for fault simulating multilevel models. In this paper, we investigate behavioral fault simulation and discuss the architecture that provides greater accuracy for a more thorough system level simulation.