Pierre Bellanger

Residual stress and dislocations density in silicon ribbons grown via optical zone melting

We investigate the relationships between growth rate, time-temperature profile, residual stress, dislocation density, and electrical performance of silicon ribbons grown via optical zone melting. The time-temperature profiles of ribbons grown at different velocities were investigated using direct measurements and computational fluid dynamics (CFD) modeling. Residual stresses up to 20 MPa were measured using infrared birefringence imaging. The effect of crystallization speed on dislocation density and residual stress is discussed from the context of thermal stresses during growth. More broadly, we demonstrate the usefulness of combining spatially resolved stress and microstructure measurements with CFD simulations toward optimizing kerfless silicon wafer quality.

New Stress Activation Method for Kerfless Silicon Wafering Using Ag/Al and Epoxy Stress-Inducing Layers

The SLIM-cut technique provides a way to obtain thin silicon foils without a standard sawing step, thus avoiding kerf losses. This process consists of three steps: depositing a stress-inducing layer on top of the silicon surface; stress activation by heating and cooling, resulting in crack propagation in the silicon and detachment of a thin silicon layer; and a chemical cleaning to remove the stress-inducing layer. This paper describes a new stress activation method using Ag/Al and epoxy stress-inducing layers. The crack propagation is controlled along the sample length in order to avoid unwanted additional crack formation and interaction with other crack fronts. Silicon foils with thickness ranging between 50 and 130 μm were obtained with effective lifetimes between 1 and 81 μs.

First Solar Cells on Exfoliated Silicon Foils Obtained at Room Temperature by the SLIM-Cut Technique Using an Epoxy Layer

In this paper, we report on the first solar cells fabricated on silicon foils employing the stress-induced liftoff methodcut technique and using an epoxy stress-inducing layer. The latter is a 900-μm-thick epoxy layer, which was manually dispensed on the surface of a monocrystalline silicon sample and cured at 150 °C for 1 h. The crack propagation is then activated by cooling down the sample to room temperature on an aluminum plate. The structural and electrical properties of the resulting silicon foils are presented. The thickness of the silicon foil and the maximum roughness height after this process are found to be around 130 and 37.4 μm, respectively. Tensile and compressive regions present in the foil were detected by the birefringence technique and indicate the formation of structural defects such as dislocations during the process. Average minority carrier lifetimes around 28 μs were measured on n-type silicon foils after surface passivation by an iodine-ethanol solution. Photon conversion efficiencies of 12.6% and 13.4% are measured using conventional sun simulator (1-sun AM1.5G) and SINTON Suns-Voc setup systems, respectively.

Room temperature thin foil SLIM-cut using an epoxy paste: experimental versus theoretical results

The stress induced lift-off method (SLIM) -cut technique allows the detachment of thin silicon foils using a stress inducing layer. In this work, results of SLIM-cut foils obtained using an epoxy stress inducing layer at room temperature are presented. Numerical analyses were performed in order to study and ascertain the important experimental parameters. The experimental and simulation results are in good agreement. Indeed, large area (5 × 5 cm2) foils were successfully detached at room temperature using an epoxy thickness of 900 μm and a curing temperature of 150 °C. Moreover, three foils (5 × 3 cm2) with thickness 135, 121 and 110 μm were detached from the same monocrystalline substrate. Effective minority carrier lifetimes of 46, 25 and 20 μs were measured using quasi-steady-state photoconductance technique in these foils after iodine ethanol surface passivation.

Comparative study of stress inducing layers to produce kerfless thin wafers by the Slim-cut technique

The decrease in wafer thickness seen as a route to cost reductions has raised a growing interest in techniques that allow the preparation of thin wafers without kerf loss. The Slim-cut process [1] is one of these new techniques and comprises mainly three stages: a stress layer deposition step on the top of a monocrystalline silicon sample, a heating step necessary to induce the stress on the silicon sample and detach a thin silicon layer, and a third step to clean the stress-inducing layer to obtain a silicon foil adapted to the fabrication of solar cells. One of the major problems of this technology consists in finding a stress layer that induces a sufficiently high contraction in order to achieve a rupture of the silicon without contamination of the foil. In this work we present a comparison between thin foils obtained by Slim-cut, using three different stress layers: i) a double screen printed Silver/Aluminum layer, ii) a dispensed epoxy paste, iii) an electrodeposited Nickel metallization. Results on lifetime measurements indicate that some of the stress layers, although capable of inducing large stress, severely degrade lifetime of the foil.