Piyali Goswami

Accelerating H.264/HEVC video slice processing using application specific instruction set processor

Video coding standards (e.g. H.264, HEVC) use slice, consisting of a header and payload video data, as an independent coding unit for low latency encode-decode and better transmission error resiliency. In typical video streams, decoding the slice header is quite simple that can be done on standard embedded RISC processor architectures. However, universal decoding scenarios require handling worst case slice header complexity that grows to un-manageable level, well beyond the capacity of most embedded RISC processors. Hardwiring of slice processing control logic is potentially helpful but it reduces flexibility to tune the decoder for error conditions - an important differentiator for the end user. The paper presents a programmable approach to accelerate slice header decoding using an Application Specific Instruction Set Processor (ASIP). Purpose built instructions, built as extensions to a RISC processor (ARP32), accelerate slice processing by 30% for typical cases, reaching up to 70% for slices with worst case decoding complexity. The approach enables real time universal video decode for all slice-complexity-scenarios without sacrificing the flexibility, adaptability to customize, differentiate the codec solution via software programmability.

Multichannel video software solution for an asynchronous multiprocessor system

Multichannel video usecases put considerable resource demands on the processing system. Software designed for single channel when extended to multichannel often does not exploit the capabilities of the system fully and limits the number of channels that can be processed simultaneously. In this paper, we discuss the performance constraints observed in an asynchronous multiprocessor system when extending a single channel codec software solution to a multichannel usecase. This is followed by a discussion on building a multichannel codec solution using the existing single channel framework by exploiting bunch submission and parallelizing the operations of different processing cores to maximize the system resource utilization. Upto 30% channel density gains are observed when migrating from the single channel to multichannel solution.

High performance automotive radar signal processing on TI's TDA3X platform

Automotive is an important application of radar. In collision avoidance applications, radar and camera are two main sensors with radar having a healthy share [16]. Usage of radar in the automotive space is expanding beyond range and velocity detection of obstacles to more sophisticated usage of object motion direction estimation [17], precise angular position estimation of obstacles in urban environments [6][7] and ground vehicle localization[15]. As a result, radar processing solutions require complex signal processing with higher programmability. In this paper, we explain the mapping of automotive MIMO radar processing chain on TIs TDA3x platform and highlight the need for a heterogeneous processor architecture with adequate programmability.

Re-target-able software power management framework using SoC data auto-generation

Heterogeneous multiprocessor SoCs (MPSoCs) are becoming very complex with greater demands for performance and low power. Advanced hardware techniques and involved software programming (>1000 registers) are employed to attain low/ultra-low power. Power management (PM) software development time is high. It is made worse with heavy rework when migrating across SoCs. In this paper we propose techniques to create a re-target-able software PM framework, independent of OS or file system, with auto-generated databases containing registers, clock tree and device power attributes from SoC IP-XACT specifications. These techniques helped achieve 90% reduction in migration time on Texas Instruments automotive and industrial MPSoCs.

Low complexity in-loop skin tone detection for ROI coding in the HEVC encoder

Perceptual video coding with rate control is a technique commonly used to improve the perceptual video quality without compromising on the video bit rate. Region of Interest (ROI) detection has traditionally been done by a dedicated software or hardware block which provides the video encoder the coordinates of the regions whose perceptual video quality needs to be higher than non-ROI regions. This paper introduces a low complexity human skin color based ROI detection technique in-loop with the HEVC encoder which classifies a coding unit as skin or not. The proposed method utilizes the HEVC encoder tools of spatial predictive encoding, variable coding unit block sizes and motion vectors generated during motion estimation to optimize skin tone detection in Intra and Inter predicted frames. The in-loop classification was found to improve the detection precision per operation per pixel by 4x compared to other low cost skin classifiers.

Thermal safety through Limp Home Mode for intelligent Rear View Camera Systems

Multiprocessor SoCs (MPSoCs) are deployed in intelligent Rear View Camera Systems (iRVCS) for capture, analytics and display. iRVCS, mounted near the cars exterior surface, are subject to direct sunlight for prolonged time. At high junction temperatures (Tj) iRVCS completely shuts down for thermal protection resulting in complete loss of visibility. The paper focuses on techniques to detect such conditions and switch to a Limp Home Mode (LHM) with basic rear view visibility. When Tj reduces, it seamlessly switches back to original usecase. Results showed the switch takes <; 350 milliseconds achieving 20-25% power savings (5°C cooler) at high ambient temperatures.