Piyush Bhatt

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation

Germanium Oxynitride (GeON) gate interlayer (IL) dielectric formed using decoupled plasma nitridation (DPN) technique is compared with GeO2 and thermally nitrided GeON ILs for Ge gate stack applications using n-channel capacitors and transistors. Lower nitrogen concentration and roughness at the GeON/Ge interface lead to lower midgap interface trap density (Dit) and 1.5× higher electron mobility for the DPN versus thermally nitrided GeON IL. DPN GeON IL also exhibits enhanced thermal stability till 575 °C at the expense of a small degradation in Dit versus GeO2 IL, making it a more viable gate IL dielectric on Ge channels.

High Performance 400 °C p + /n Ge Junctions Using Cryogenic Boron Implantation

We report high performance Ge p⁺/n junctions using a single, cryogenic (-100 °C) boron ion implantation process. High activation>4 × 10²⁰ cm^-3 results in specific contact resistivity of 1.7 × 10^-8 Ω-cm² on p⁺-Ge, which is close to ITRS 15 nm specification (1 × 10^-8 Ω-cm²) and nearly 4.5× lower than the state of the art (8 × 10^-8 Ω-cm²). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p⁺/n junctions can pave the way for future high mobility Ge p-MOSFETs.

Enhanced Ge n + /p Junction Performance Using Cryogenic Phosphorus Implantation

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (-100 °C) implantation with a dose of 2.2e15 cm-2 followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 cm-2) exhibit lower OFF-current (upto 5x) and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (-100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge.

Bio-interfacing of resonant transmission characteristics of InSb-based terahertz plasmonic waveguide

We have investigated, both experimentally and numerically, the transmission of terahertz (THz) electromagnetic waves in indium antimonide waveguides with stubs along the waveguide. The resonant transmission characteristics of the device at THz frequencies are exploited for sensing biological samples. The transmission characteristics of the waveguide were simulated using finite element method techniques for various sizes of waveguide width and stub length. The waveguides were fabricated by laser micromachining, and their transmission characteristics were measured by terahertz time-domain spectroscopy. The experimental results are consistent with the simulation results. The stubs of the device were loaded with bovine serum albumin (BSA) protein molecules dissolved in water. A significant change in the THz transmission coefficient was observed for different concentrations of BSA, thus indicating the potential of the device for bio-sensing. The calculated absorption coefficients of the BSA samples agree well with the reported ones.

Optimization of a plasma immersion ion implantation process for shallow junctions in silicon

A plasma immersion ion implantation (PIII) process has been developed for realizing shallow doping profiles of phosphorus and boron in silicon using an in-house built dual chamber cluster tool. High Si etch rates observed in a 5% PH3 in H2 plasma have been ascribed to high concentration of H(α) radicals. Therefore, subsequent work was carried out with 5% PH3 in He, leading to much smaller etch rates. By optical emission spectroscopy, the radical species H(α), PH*2, and PH* have been identified. The concentration of all three species increased with pressure. Also, ion concentrations increased with pressure as evidenced by Langmuir data, with a maximum occurring at 0.12 mbar. The duty cycle of pulsed DC bias has a significant bearing on both the implantation and the etching process as it controls the leakage of positive charge collected at the surface of the silicon wafer during pulse on-time generated primarily due to secondary electron emission. The P implant process was optimized for a duty cycle of 10% ...

Temperature and field dependent low frequency noise characterization of Ge n-FETs

We report temperature (RT-150 K) and field dependent low frequency noise measurements on Ge n-FETs. Specifically, we delineate the temperature, field, and interfacial layer (GeON vs. GeO2) dependence of the gate overdrive index (β) on corresponding changes in volume interface trap density (Nit) and mobility (μ). For Nit   1 × 1020 cm−3eV−1 near the conduction band edge, changes in μ as well as Nit determine the noise mechanism. Finally, we show that the β values of Ge n-FETs are significantly different from conventional Si transistors as well as Ge p-FETs at RT and 150 K due to much higher Nit and/or μ values of the Ge n-FETs.

Ge n + /p junctions using temperature-based phosphorous implantation

This work compares the impact of implantation temperature ranging from cryogenic (-100 °C) to hot (400°C) on the performance of n+/p Ge junctions. Cryogenic implantation on bulk, planar Ge followed by a 400°C rapid thermal anneal leads to higher activation. lower junction depth, lower sheet resistance and lower junction leakage compared to RT and hot (400°C) implantation. The improved junction performance translates into higher ON current and lower OFF leakage for cryo implanted planar Ge n-MOSFETs. On the other hand, high dose/energy cryogenic implants on Ge fins are shown to degrade fin recrystallization due to the absence of a crystalline core because of increased amorphization. Crystallinity of as-implanted Ge fins indicates that hot implantation could be a more viable n+/p junction formation process for Ge FinFET technology.

Cryo implanted high performance n + /p junctions in Ge for future CMOS

This work demonstrates high performance n+/p Ge junctions using cryo (-100°C) ion implantation of phosphorus, followed by a low temperature (400°C) anneal. Improvements such as higher dopant activation (21.3% vs. 14.5%), lower junction leakage due to less end-of-range damage (3.9A/cm2 vs. 11.6A/cm2), lower junction depth (220nm vs. 270nm) and lower sheet resistance (65Ω/□ vs. 87Ω/□) are demonstrated for cryo vs. room temperature (RT) phosphorus implanted n+/p junctions. Compared to RT, 7.5X reduction in off-state leakage is demonstrated on Ge nMOSFETs fabricated using a gate last process with cryo implanted junctions. Phosphorus activation is also demonstrated on cryo implanted, 25 nm wide Ge fins indicating feasibility of this process for future Ge CMOS technology.

Performance comparison of MIM and MIS diodes for energy harvesting applications

Scavenging energy from electromagnetic waves is one of the emerging areas for low-power energy harvesting. The wave is received by an antenna and is then rectified using nonlinear devices for generating required DC voltages. In addition to the traditional diodes other rectifying elements with different structures are exploited to get reduced turn-on voltage and enhanced operating frequency range. For example metal-insulator-metal (MIM) diodes, which work on the principles of the quantum mechanical tunneling, are able to rectify the signals. In this direction this paper presents fabrication and characterization of tunneling-based rectifying MIM, metal-insulator-semiconductor (MIS) and metal-semiconductor (MS) Schottky diodes. Presented MIM tunnel diodes are made using Ti-TiO2-Al and Ti-TiO2-Pt stacks, while MIS and MS diodes are fabricated using Si as well as Ge substrates. Measurement results show that Ge p+n and Si MIS provide higher output DC voltage as compared to Si pn diodes. MIM diodes operate at a wider frequency range as compared to other devices.

Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs

We demonstrate record boron activation >4×10²⁰cm^-3 and contact resistivity of 1.7×10^-8Ω-cm² on p⁺-Ge using a single boron implantation process step at cryogenic temperature followed by a low temperature (400^oC) activation anneal. Unlike RT and hot (400^oC) implantation, cryogenic implantation also gives shallower junctions (maintaining lower R_sh) and higher I_ON/I_OFF ratio. Fin TEM and electrical data as well as device simulations for cryogenic, low energy BF₂ implanted epitaxial Ge fins indicate significant and scalable improvement in dopant activation vs room temperature implantation demonstrating feasibility of cryogenic implants for source/drain extensions of future 3D Ge channel p-FinFETs.