Po-Hao Wang

Strain relaxation in In0.2Ga0.8As/GaAs quantum-well structures by x-ray diffraction and photoluminescence

The onset of strain relaxation in In0.2Ga0.8As/GaAs quantum-well structures is investigated. X-ray diffraction shows that when the InGaAs thickness increases beyond its critical thickness, another peak on the right shoulder of the GaAs peak appears, indicating that the top GaAs layer is being compressed in the growth direction by the relaxation of the InGaAs layer. Energy shifts of 44 and 49 meV are observed, respectively, from the strains of the InGaAs and GaAs top layers when increasing the InGaAs thickness from 300 and 1000 A. These energy shifts are in agreement with theory calculated based on the relaxation process observed in x-ray diffraction, providing evidence that the relaxation occurs from near the bottom InGaAs/GaAs interface while the top interface still remains strained. This result is further corroborated by the images of cross-sectional transmission electron micrographs which show that most of the misfit dislocations are confined near the bottom interface.

Carrier depletion by defects levels in relaxed In0.2Ga0.8As/GaAs quantum-well Schottky diodes

An increase in leakage current accompanied by a drastic carrier depletion is found for InGaAs/GaAs Schottky diodes when the InGaAs thickness is larger than its critical thickness. Due to drastic carrier depletion, free-carrier concentration around the InGaAs region for relaxed samples cannot be obtained from capacitance–voltage data but from resistance–capacitance time constant effect observed in capacitance–frequency measurement. A trap at 0.33 to 0.49 eV is observed for relaxed samples by deep-level transient spectroscopy. The resistance caused by carrier depletion has an activation energy close to that of the trap, supporting that the carrier depletion is caused by capture from the trap.

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

Variation-aware and adaptive-latency accesses for reliable low voltage caches

Contemporary cache is known for consuming a large part of total power in microprocessors. Voltage scaling had been used to reduce the power consumption of the cache. However, due to the impact of variations, SRAM cells of the cache could potentially fail when voltage dropping. To against variations, we need to increase the supply voltage for the safety margin, thus the cache costs large energy consumption. For eliminating the voltage safety margin, some prior works for SRAM failure tolerance designs were proposed. These schemes will result in worse energy consumption and cannot deal with dynamic variations. They still have a safety margin to resist dynamic variations. With the supply voltage scaling down, we find out that the major reason of failures is that some slow cells have longer latency. We call these cell faults as “latency fault”. If each cache line can be accessed in an appropriate access time, the slower cells could be reused but not disable them. We propose a VAL-Cache adapting the access time to tolerate latency faults and which is able to scale down the voltage. And we also propose the latency-fault detector to detect latency faults at run-time so as to tolerate both static and dynamic variations. Our experimental results on Mibench and 0xbench benchmarks demonstrate that the energy consumption can be reduced 10%~18% in average at a cost of acceptable performance loss.

Observation of carrier depletion and emission effects on capacitance dispersion in relaxed In0.2Ga0.8As/GaAs quantum wells

Strong changes in capacitance over frequency are found for highly relaxed In0.2Ga0.8As/GaAs quantum well. The high-frequency dispersion is explained by a resistance–capacitance time constant effect due to the existence of a high resistive layer while the low-frequency dispersion is due to carrier emission from traps. The high-resistance layer is created by carrier depletion when InGaAs thickness increases beyond the critical thickness. Excellent agreement is found between the data from capacitance–frequency spectra and deep-level transient spectroscopy, permitting us to conclude that both the carrier depletion and emission effects observed in capacitance–frequency spectra are due to the existence of an acceptor trap at 0.33 eV. This trap is generated when the InGaAs thickness is beyond its critical thickness and is due to defect states associated with misfit dislocations.

Electrical characteristics and deep-level admittance spectroscopies of low-temperature grown GaAs p-i-n structures

The properties of low-temperature grown GaAs are studied via the electrical characterization of p-i-n structures with part of the intrinsic layer grown at 300 °C. Comparisons are made between the low-temperature and normally grown samples. The current of the low-temperature sample is about two orders of magnitude higher than that of the normally grown sample in both forward and reverse bias. From temperature-dependent analysis, the leakage current of the low-temperature sample is contributed by the recombination current through defect levels around the midgap, from which a recombination lifetime of 9.4×10−12 s was obtained. By using admittance spectroscopy we observed a dominant electron level at 0.60 eV with a corresponding capture cross section of 1.0×10−13 cm2 that was not observed in the normally grown sample; thus it is believed to be introduced by the As-rich low-temperature layer.

Effect of growth temperature on the electric properties of In0.12Ga0.88As/GaAs p-i-n multiple-quantum-well diodes

The electric properties of In0.12Ga0.88As/GaAs p-i-n multiple-quantum-well (MQW) diodes, with the MQW layer grown at different temperatures by molecular beam epitaxy, have been investigated. Temperature-dependent current–voltage studies reveal a trap-filled limit current at a low temperature and a generation-recombination current via deep levels at high temperature for a 300 °C-grown sample. Frequency-dependent capacitance and deep-level transient spectroscopy reveal one majority trap at 0.73 eV and two minority traps at 0.71 and 0.43 eV. The 0.73 eV trap is also detected in 550 °C-grown samples, suggesting that it is a common defect in relaxed InGaAs/GaAs MQWs and probably originates from the defect states related to the strain relaxation. The 0.71 eV trap is believed to be the dominating deep level that governs the current conduction due to the activation energy observed in the current–voltage characteristics.

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures

An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The poor performance of an ultralow-voltage core causes most workload requirements to awaken and then execute on the host core, leading to high energy consumption. In this paper, we propose a ULV-Turbo cache based on a ULV-selective-ally 8T static random access memory (SRAM) that is able to perform reliable ultralow-voltage operation and provide the speedup function of SRAM rows ally. The system is able to speed up the ULV core instantaneously and execute more applications with the ULV-Turbo cache. In our system-wide evaluation based on a real attitude and heading reference system workload on an asymmetric wearable system, the ULV-Turbo cache reduces the energy consumption of the entire system by approximately 36%.

Cross-matching caches

Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. The timing gap between cache and core harms the performance of whole system.Values stored in 8T SRAM influences the read latency of the cache.Adjusting the read latency with different stored data to reduce the timing gap.A bit-level timing fault mask to tolerate numerous slow cells caused by timing gap.

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations

In modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. This study investigates the characteristics of low-voltage 8 T SRAM faults and demonstrates that most SRAM faults are typically caused by insufficient access times with variation effects and significantly reduced voltages. Thus, we propose an access-time fault-tolerant cache design based on a type of 8 T SRAM known as zero-counting and adaptive-latency cache (ZCAL cache), which can tolerate numerous access-time faults. ZCAL caches detect access-time faults dynamically using a lightweight error detection code (“0” counting) because access-time faults occur only when reading “0” bits on the 8 T SRAM; the cache then adapts its access time to tolerate the access-time faults with new cache management processes. With the ZCAL cache, the experimental results from the MiBench benchmarks indicate that the energy efficiency is improved by 17% on average and that the energy consumption is reduced by 22% from 0.76 to 0.63 V.