Jinn-Shyan Wang

Low-voltage pulsewidth control loops for SOC applications

The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-/spl mu/m CMOS process with only 1.8-V V/sub DD/ successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory

A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264

This paper proposes a high-performance direct two-dimensional transform coding IP design for MPEG-4 AVC/H.264 video coding standard. Because four kinds of 4 /spl times/ 4 transforms, i.e., forward, inverse, forward-Hadamard, and inverse-Hadamard transforms are required in a H.264 encoding system, a high-performance multitransform accelerator is inevitable to compute these transforms simultaneously for fitting real-time processing requirement. Accordingly, this paper proposes a direct 2-D transform algorithm which suitably arranges the data processing sequences adopted in row and column transforms of H.264 CODEC systems to finish the data transposition on-the-fly. The induced new transform architecture greatly increases the data processing rate up to 8 pixels/cycle. In addition, an interlaced I/O schedule is disclosed to balance the data I/O rate and the data processing rate of the proposed multitransform design when integrated with H.264 systems. Using a 0.18-/spl mu/m CMOS technology, the optimum operating clock frequency of the proposed multitransform design is 100 MHz which achieves 800 Mpixels/s data throughput rate with the cost of 6482 gates. This performance can achieve the real-time multitransform processing of digital cinema video (4096 /spl times/ 4 2048@30 Hz). When the data throughput rate per unit area is adopted as the comparison index in hardware efficiency, the proposed design is at least 1.94 times more efficient than the existing designs. Moreover, the proposed multitransform design can achieve HDTV 720p, 1080i, digital cinema video processing requirements by consuming only 0.58, 2.91, and 24.18 mW when operated at 22, 50, and 100 MHz with 0.7, 1.0, and 1.8 V power supplies, respectively.

Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops

This paper describes the design of a low-power pipelined multiplier. It is illustrated in this paper that the power consumption of the clocking system cannot be overlooked and the design of the storage element is the key to low power. A new pulse-triggered true single-phase clocking (TSPC) flip-flop (PTTFF) is proposed for this purpose in this design. The PTTFF features true single-phase clocking, simple structure, and high performance. One PTTFF comprises only five transistors with only one controlled by the clock. Using the PTTFF together with the 14-transistor pseudo-NMOS full adder, an 8-b/spl times/8-b pipelined multiplier has been designed and implemented, employing a 0.6-/spl mu/m CMOS process. When the multiplier operates at the operating frequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% of the power of the multiplier designed with nine-transistor TSPC flip-flops under the same operating conditions. When the supply voltage for the core array is reduced to 2.5 V, the multiplier can still work up to 300 MHz with only 47% of the power of the multiplier designed using the S and D full adders and C/sup 2/MOS latches with VDD equal to 3.3 V. The chip has been fabricated, and the measured power is 52.4 mW when operated at 300 MHz and 3.3 V.

An ultra-low-power fast-lock-in small-jitter all-digital DLL

Using binary-weighted differential-delay cells and an asynchronous binary search circuit, the proposed 1.0V 0.25 /spl mu/m all-digital DLL achieves nearly 2 orders of magnitude reduction in power consumption, a 36% reduction in jitter, and a 33% reduction in locking cycles, compared to conventional fast-lock mixed-mode DLL.

High-Speed and Low-Power Design Techniques for TCAM Macros

Ternary content addressable memory (TCAM) is an important component for many applications. For TCAM-based networking systems, the rapidly growing size of routing tables brings with it the challenge to design higher search speeds and lower power consumption. In this work, two techniques are proposed to realize high-performance and low-power TCAM for IP address lookup. One technique is the tree AND-type match-line scheme for high search speed. The other technique is the segmented search-line scheme for low power. The implemented 1.8 V 0.18 mum 256 times 128b TCAM macro achieves a 1.56 ns search time using a 1.42 fJ/bit/search of energy.

An AND-type match-line scheme for high-performance energy-efficient content addressable memories

High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 /spl times/ 128-b CAM macro, based on a 0.18-/spl mu/m 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 /spl times/ 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 /spl times/ 128-b CAM macro, based on a 0.18-/spl mu/m 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 /spl times/ 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.

Analysis and design of high-speed and low-power CMOS PLAs

The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are analyzed first to find out their speed and power bottlenecks. Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time. Finally, high speed is achieved through the combined effect of utilization of a fast pseudofootless dynamic circuit and a reduced interplane clock delay. On the other hand, low power is achieved because the power consumption from the three main sources, i.e., the AND-plane circuits, the interplane buffers, and the OR-plane circuits, can be reduced significantly and simultaneously. The delay time and the power consumption of the critical path of a PLA are taken as the performance evaluation parameters. When the 50/spl times/50/spl times/64 PLAs are designed in a 0.35-/spl mu/m 1P4M CMOS technology, the maximum operating frequency of the proposed PLA is 1.61 times higher than that of the fastest conventional PLA. Furthermore, power reduction can be as high as 18% and 43% when the operating frequencies are set to be 100 MHz and 50 MHz, respectively, as compared to the most power-efficient conventional PLA.

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ¿W/MHz power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications

This paper proposes a dynamic quality-adjustable H.264 baseline profile (BP) video encoder that comprises 470 Kgates and 13.3 kB SRAM in a core size of 4.3 × 4.3 mm2 using TSMC 0.13 ¿m 1P8M CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. In addition, the proposed basic unit (BU)-based rate control hardware can maintain a constant and stable bit rate for network video transmission. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30 frames/s with 7 mW to 25 mW, 27 mW to 162 mW, and 122 mW to 183 mW power dissipation in different quality modes.