Po-Hung Chen

An effective output-oriented algorithm for low power multipartition architecture

Circuit partition for low power is a useful technique which reduces power dissipation by confining the switching activity to a subcircuit. In this paper, we propose an effective output-oriented partition algorithm for low power combinational logic circuits. We discuss the relationship between power dissipation, area complexity and input/output behavior of the combinational circuit rather than inspect its logic function. Experimental results show that our algorithm can obtain sizable power saving over a wide range of MCNC benchmarks.

Unambiguous BPSK-like CSC method for Galileo acquisition

Galileo will be Europes own Global Navigation Satellite System (GNSS), which is aiming to provide highly accurate and guaranteed positioning services. Galileo E1 system has a code period of 4ms which is quadruple that of GPS C/A code. In other words, due to the large number of hypotheses in code phase at acquisition stage, a longer searching time or more hardware resource is required. It is difficult to acquire Galileo signal because of longer code length and the multiple peaks of autocorrelation function of BOC modulation. In this paper, the cyclically shift-and-combine (CSC) and BPSK-like architectures are employed to resolve the unambiguous acquisition for BOC modulation and acquires these satellite signals with hardware complexity reduction. The concept of CSC code is to modify the code structure and shorten the code period such that the acquisition burden can be decreased. Simulation results show that our proposed search algorithm can provide better performances in terms of low hardware complexity for acquiring these satellite signals and detection probability at the low value of CNR.

Adaptive fast block mode decision algorithm for H.264/AVC

H.264/AVC outperforms the previous coding standards thanks to variable block size motion compensation (VBSMC) ranging from 4×4 to 16×16 in interframe coding. However, this new feature causes extremely high computation complexity when rate-distortion optimization(RDO) is performed using full mode decision. In this paper, we propose an adaptive fast block mode decision algorithm (AFBMD) leveraging the following characteristics to significantly reduce the complexity. (1) detecting stationarity of a block by using sum of absolute difference (SAD) and the biggest pixel difference. (2) exploiting the left and upper block modes to determine the block mode priority order. (3) comparing the RDcosts of the current best block mode and the block modes in the priority order that attempt to early terminate the block mode decision. Compared with the full mode decision (FMD) [20], the experimental results shown that the proposed algorithm reduces the mode decision complexity up to 77% while still maintains almost the same image quality as FMD.

The UKF-based RNN predictor for GPS narrowband interference suppression

The global positioning system (GPS) provides accurate positioning and timing information useful in many applications. Although DS-SS inherently can cope with low power narrowband and wideband obstacles by its near 43-dB processing gain, it cannot cope with high power obstacles. The approaches of system performances that can be further enhanced by preprocessing to reject the intentional or unintentional jamming will be investigated in this paper. A recurrent neural network (RNN) predictor for the GPS anti-jamming applications will be proposed. The adaptive RNN predictor is utilized to accurately predict the narrowband waveform based on an unscented Kalman filter (UKF)-based algorithm. The UKF is adopted to achieve better performance in terms of convergence rate and quality of solution. Two types of narrowband interference, i.e. continuous wave interference (CWI) and auto regressive interference (ARI), are considered to emulate realistic circumstances. The signal-to-noise ratio (SNR) is varied from -20 to -5 dB. The anti-jamming performances are evaluated via extensive simulation by computing mean squared prediction error (MSPE) and signal-to-noise ratio (SNR) improvements.

Content-adaptive thresholding early termination scheme on directional gradient descent searches for fast block motion estimation

Abstract. An efficient algorithm named modified directional gradient descent searches to enhance the directional gradient descent search (DGDS) algorithm is presented to reduce computations. A modified search pattern with an adaptive threshold for early termination is applied to DGDS to avoid meaningless calculation after the searching point is good enough. A statistical analysis of best motion vector distribution is analyzed to decide the modified search pattern. Then a statistical model based on the characteristics of the block distortion information of the previous coded frame helps the early termination parameters selection, and a trade-off between the video quality and the computational complexity can be obtained. The simulation results show the proposed algorithm provides significant improvement in reducing the motion estimation (ME) by 17.81% of the average search points and 20% of ME time saving compared to the fast DGDS algorithm implemented in H.264/AVC JM 18.2 reference software according to different types of sequences, while maintaining a similar bit rate without losing picture quality.

An unified architecture of all transforms for H.264/AVC codec

In this paper, an unified hardware architecture for the complete set of transforms in H.264/AVC codec is presented. This architecture has been mapped into 2-D 4×4 forward/inverse transforms, 2-D 4×4/2×2 Hadamard transforms, and 1-D 8×8 forward/inverse transforms resulting in 31 sub/adders, 7 adders, 6 subtractors, 34 shifter, 4 multiplexer, and 16 registers. The architecture calculates 16 inputs and 8 outputs in parallel for 4×4 integer forward/inverse transforms, and 8 inputs and 8 outputs in parallel for 8×8 integer forward/inverse transforms by our proposed fast 4-step process. The register array is not necessary for transpose operations of 4×4 forward/inverse and 4×4/2×2 Hadamard transforms. With 8 pixels/cycle throughput, the proposed design can complete the computation in 50 clock cycles with 8×8 and 4×4 transforms for one macroblock in 4:2:0 format.

Center of mass-based adaptive fast block motion estimation

This work presents an efficient adaptive algorithm based on center of mass (CEM) for fast block motion estimation. Binary transform, subsampling, and horizontal/vertical projection techniques are also proposed. As the conventional CEM calculation is computationally intensive, binary transform and subsampling approaches are proposed to simplify CEM calculation; the binary transform center of mass (BITCEM) is then derived. The BITCEM motion types are classified by percentage of (0,0) BITCEM motion vectors. Adaptive search patterns are allocated according to the BITCEM moving direction and the BITCEM motion type. Moreover, the BITCEM motion vector is utilized as the initial search point for near-still or slow BITCEM motion types. To support the variable block sizes, the horizontal/vertical projections of a binary transformed macroblock are utilized to determine whether the block requires segmentation. Experimental results indicate that the proposed algorithm is better than the five conventional algorithms, that is, three-step search (TSS), new three-step search (N3SS), four three-step search (4SS), block-based gradient decent search (BBGDS), and diamond search (DS), in terms of speed or picture quality for eight benchmark sequences.

Markov model fuzzy-reasoning based algorithm for fast block motion estimation

Abstract This paper presents a Markov model fuzzy-reasoning based algorithm for fast block motion estimation. To reduce computational complexity, the existing fast search algorithms move iteratively toward the winning point based only on a finite set of search points in every stage. Despite the efficiency of these algorithms, the search process is easily trapped into local minima, especially for high activity video sequences. To overcome this difficulty, we propose a three-states Markov model based algorithm that invokes the fuzzy-reasoning to provide the search an acceptance probability of being able to move out of local minima. Two schemes are employed to further enhance the performance of the algorithm. First, a set of initial search points that exploit high correlations among the motion vectors of the temporally and spatially adjacent blocks as well as their surrounding points are used. Second, an alternate search strategy is addressed to cover more area without increasing computations. Simulation results show that the new algorithm offers superior performance with lower computational complexity and picture quality increase in terms of search points/block and MSE/pel, respectively, compared with the previous works in various scenarios.

Designing platform-based system power management on a smart tablet appliance

For the design of portable systems, power consumption is as important a design criterion as performance. Low power design starts at the system level and a top down approach will yield the greatest results. Previous researches only address on partial stages of platform-based power management. Hence, in this paper, we consider the low power design on the whole system to explore the methodology and implementation from the circuit design stage including selection of key components, analysis of hardware architecture and the platform design to dynamic power management on battery management techniques, operating systems and software design for various Hardware/Software co-design issues. We will take the tablet appliances platform as an example to illustrate how to design the power management system of the handheld device of medium to large sizes, and how to implement the advanced software power management mechanism on embedded OS like Microsoft Windows CE.NET.

Synthesis of partition-codec architecture for low power and small area circuit design

Partitioning circuits for low power design at the logic level has been proposed as a very effective technique. However, the increased area of latches for duplicated input of multiple partitions always offsets the advantage. In this paper we propose a novel Partition-Codec Architecture to achieve low power and small area. The approach is based on evenly partition the output vectors by the corresponding input variables and re-assigning the output vectors of each partition to minimize the number of input vectors and Hamming distance of each partition, and one of the active decoders returns the value to its original output. Given a combinational circuit described by PLA, we develop a global-encoding algorithm, which consists of partition and re-assigning routines to synthesize the Parition-Codec Architecture to achieve low power and small area. Experimental results show that up to 69.5% power reduction, as well as 60.9% area decreased and average 35.7% power saving with 58.4% area reduction are achievable.