Po-Wen Su

Self-assembled hexagonal Au particle networks on silicon from Au nanoparticle solution

Self-assembled hexagonal Au particle networks, 2–12 μm in cell size, on silicon have been achieved by a simple method. Honeycomb structure of Au nanoparticles on silicon was drop cast from the Au nanoparticle solution under appropriate concentration, evaporation rate, substrate temperature, and humidity. Hexagonal networks with discrete Au particles were generated in samples annealed in N2 ambient. Two-step annealing, i.e., annealing at 400 °C followed by annealing at 1000 °C for 1 h each was found to be effective to improve the regularity of the Au particle network. As the cell size can be adjusted by the tuning of the deposition conditions, the scheme promises to be an effective patterning method without complex lithography.

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thin-film transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 103 P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.

Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO

This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO₂ charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si₃N₄ charge-trapping layer was also fabricated. Since HfO₂ has a deeper conduction band than Si₃N₄, the device with the HfO₂ charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si₃N₄ charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO₂ charge-trapping layer to undergo more P/E cycles than that with the Si₃ N₄ charge-trapping layer.

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Hierarchical growth of silicate nanowires on individual Au particles in self-organized hexagonal Au particle networks has been achieved by appropriate control of annealing conditions in N2 ambient. Cathodoluminescence data showed that the silicate nanowires emit light with a wavelength of 415nm. The scheme to form the regular Au particle network offers an effective and economical means to produce a universal template to grow functional structures without complex lithography.

Charge Trapping Layer

This study investigates the performance improvement of the polycrystalline silicon nanowires twin thin-film transistors nonvolatile memory (poly-Si NWs twin-TFT NVM) by NH 3 and H 2 plasma treatment. The NWs twin-TFT NVM exhibits superior gate control because its tri-gate structure provides a large memory window (ΔV th ) and high program/erase (P/E) efficiency. Additionally, the proposed twin-TFT NVM scheme has effective NH 3 and H 2 plasma passivation efficiency due to its split nanowire channels structure. As for characteristics of transistors, passivation by both NH 3 and H 2 plasma increases the mobility and the I on /I off ratio. Moreover, as for characteristics of NVM, they increase ΔV th , P/E speed and improve the reliability of the devices. Comparing channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling programming mechanisms reveals that the device with NH 3 plasma passivation can significantly enhance the program speed. This ability is attributed to passivation of the defects in both the grain boundaries of the poly-Si channel and the Si/SiO 2 interface by hydrogen and nitrogen radicals, respectively. As for reliability results, the NH 3 plasma-passivated NVM device has memory windows of 1.7 and 3.8 V after 10 3 P/E cycles and for ten years of data storage, respectively.

Growth of light-emitting silicate nanowires on individual Au particles in self-assembled hexagonal Au particle networks

This work studies the two-bit effect of trigate nanowires polycrystalline silicon thin-film transistors with silicon-oxide-nitride-oxide-silicon nonvolatile memory. The two-bit effect is clearly demonstrated by the localized charge trapping in a nitride layer. The programing operation is performed by channel hot electrons injection, and erasing is performed by channel hot holes injection. The threshold voltage shifts between forward read and reverse read schemes is 2.2V. At a large gate length of 5μm, the programing is dominated by Fowler–Nordheim tunneling, resulting in the absence of two-bit storage capacity. Regarding the two-bit programing and erasing speed characteristics, one-bit programing or erasing does not affect the other bit.

Improving the Performance of Nanowires Polycrystalline Silicon Twin Thin-Film Transistors Nonvolatile Memory by NH3 Plasma Passivation

This work demonstrates a polycrystalline silicon (poly-Si) thin-film flash nonvolatile memory (NVM) that utilized Pi-shaped gate (Pi-gate) multiple nanowire channels with an HfO2 charge trapping layer. The Pi-gate nanowires (NWs) flash NVM has higher program/erase (P/E) efficiency than the conventional memory with single-channel (SC) structure. This high P/E efficiency is due to the better gate control of the Pi-gate structure. As a result of the high P/E speed, up to 105 P/E cycles can be realized. The HfO2 charge trapping layer has a deep conduction band and spatial isolated traps. These characteristics result in good data retention, only 10% charge loss after 109 s.

Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics

Program/erase characteristics of twin Poly-Si Thin Film Transistors (TFTs) EEPROM utilizing tri-gate nanowires (NWs) was demonstrated. The NWs TFT has superior gate control due to its tri-gate structure leads to higher memory window and efficiency than single-channel (SC) one. The device different gate lengths characteristics and reliability were also addressed. The capacitance ratio of proposed device of 4:1 shows optimum value in P/E operation. The present work illustrates the possibility for future system-on-panel (SOP) and 3D Flash memory application.