Min-Feng Hung

High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory

Nonvolatile memory (NVM) that is based on gate-all-around (GAA) and polycrystalline silicon (poly-Si) nanowires structure with silicon nanocrystals (NCs) as the storage nodes is demonstrated. The GAA poly-Si–SiO2–Si3N4–SiO2–poly-Si (SONOS) NVMs are also fabricated and compared. The GAA NCs NVMs have a 4.2 V of threshold voltage shift at 18 V for 1 ms, and are faster than the GAA SONOS NVMs do. In reliability studies, this NVM shows superior endurance after 104 program/erase (P/E) cycles, and loses only 14% of its charges lose after ten years at 85 °C.

Twin Thin-Film Transistor Nonvolatile Memory With an Indium–Gallium–Zinc–Oxide Floating Gate

A polycrystalline silicon (poly-Si) channel twin thin-film transistor (twin-TFT) nonvolatile memory (NVM) device with In-Ga-Zn-O<i>x</i> (IGZO) as a storage layer is demonstrated. IGZO-FG twin-TFT NVM exhibits a large memory window Δ<i>V</i>_th. A <i>V</i>_CG at 18 V for 10 ms can achieve 5.6 V of Δ<i>V</i>_th. An extrapolation of the memory window to ten years demonstrates that the stored charge still remains 65% of its initial value. Coupling ratio effect and gate length effect are discussed in detail. Such a low-temperature IGZO-FG twin-TFT NVM device is feasible for integration in IGZO-based display circuits for system-on-panel applications.

Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium–Gallium–Zinc–Oxide Charge-Trapping Layer

This letter introduces a polycrystalline silicon (poly-Si) thin-film nonvolatile memory (NVM) with a nanocrystal (NC) indium-gallium-zinc-oxide (IGZO) charge-trapping layer. Experimental results indicate that this NVM exhibits high and symmetric program/erase speeds through the Fowler-Nordheim tunneling mechanism. The memory window loss of the NVM with NC IGZO charge-trapping layer is 25% after 104 s at 85°C due to deep quantum well, as well as high-density and deep trap sites in NC IGZO charge-trapping layer. Accordingly, a poly-Si thin-film transistor with NC IGZO charge-trapping layer is promising for NVM applications.

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thin-film transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 103 P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.

Performance Enhancement of Nanowire Tunnel Field-Effect Transistor With Asymmetry-Gate Based on Different Screening Length

This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 ×10-16 A/μm) and a high ON-state current (2.47 ×10-5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 1010 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication.

Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (TCH) and gate length (LG). These devices (LG = 0.5 μm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high ION/IOFF current ratio (106A/A) and practically negligible drain-induced barrier lowering (~0 mV/V). The ION current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

High-Performance Gate-All-Around Poly-Si Thin-Film Transistors by Microwave Annealing With NH

This paper introduces nanoscale gate-all-around (GAA) n-MOS polycrystalline silicon thin-film transistors (poly-Si TFTs) by using microwave annealing (MWA). Experimental results of MWA GAA poly-Si TFTs indicate high performances with subthreshold swing (SS) of 105 mV/dec., and ION/IOFF ratio of 107 A/A. MWA reveals sufficient dopant activation efficiency, which is equivalent to rapid thermal annealing. Additionally, the short channel effect is reduced owing to the low-temperature process of MWA and superior gate control of the GAA structure. Moreover, using NH3 plasma treatment further improves the device mobility, ION/IOFF ratio, and SS. Importantly, the proposed MWA GAA poly-Si TFT with its high performance and low-temperature process is highly promising for advanced 3-D ICs.

_{\rm 3}

This work demonstrates the feasibility of a charge-trapping nonvolatile memory based on Pi-gate polycrystalline silicon tunneling field-effect transistor, which has a silicon-oxide-nitride-oxide-silicon structure. Both the conducting current and the program/erase operations are based on quantum tunneling. In addition to a large threshold voltage shift of 4.7 V when Vg of 17 V is applied for only 1 ms, the proposed nonvolatile memory exhibits superior endurance of 88% after 104 P/E cycles. Moreover, only 35% of its initial charges are lost after ten years at a high temperature of 85 °C.

Plasma Passivation

This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO₂ charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si₃N₄ charge-trapping layer was also fabricated. Since HfO₂ has a deeper conduction band than Si₃N₄, the device with the HfO₂ charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si₃N₄ charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO₂ charge-trapping layer to undergo more P/E cycles than that with the Si₃ N₄ charge-trapping layer.

Pi-gate tunneling field-effect transistor charge trapping nonvolatile memory based on all tunneling transportation

This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.