Pontus Åström

Application of Software design patterns to DSP library design

The design of a hardware data path library is one of the harder problems in design for reuse. Due to the appearance of hardware modeling libraries based on C++, it is possible to apply advanced software techniques to design such a library. This paper shows how software design patterns can be applied to hardware design. Design patterns yield a twofold advantage: a faster design process, and a library that is more extensible and modular than an equivalent HDL counterpart. From a VHDL-C++ design comparison we found that those factors might result in a reduction of the code size by a factor of two.

Power Reduction in Custom CMOS Digital Filter Structures

Today the main optimization parameter of digital filters is the filter order. By the aid of two implemented filters we will show that both power and speed can be enhanced if the optimization effort is made on reducing the filter coefficient lengths rather than minimizing the order. Both filters have been designed from the same specification, one as a standard minimum order filter, the other as a filter with short coefficients found by a computer search. The minimum order filter is of order three with seven bits long coefficients. The coefficient optimized filter is of order six with two bits long coefficients. Both filters were implemented with bit-serial fixed coefficient arithmetic in twos complement representation in a 0.8µ, two metal layers CMOS process. Measurements show an eightfold speedup at half the power consumption and only 30% area cost for the coefficient optimized filter.

Dual supply-voltage scaling for reconfigurable SoC's

By partitioning a hardware design into several blocks and adjusting the voltage of the different blocks individually, an overall power consumption reduction is possible. An algorithm and a hardware solution for assigning two supply voltages to a design divided into blocks is presented. The two supply voltages are optimized using an on-chip controller. The on-chip controller assigns one of the two supply voltages to each block. This defines a solution suitable for reconfigurable designs.

Low power optimization of bit-serial digital filters

A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.