Thomas Olsson

Supporting Roadmapping of Quality Requirements

Would slightly better performance be significantly more valuable from a market perspective? Would significantly better performance be just slightly more expensive to implement? When dealing with performance, usability, reliability, and so on, you often end up in difficult trade-off analysis. You must take into account aspects such as release targets, end-user experience, and business opportunities. At the same time, you must consider what is feasible with the evolving system architecture and the available development resources.Quality requirements are of major importance in the development of systems for software-intensive products. To be successful, a company must find the right balance among competing quality attributes. How should you balance, for example, investments for improved usability of a mobile phones phone book and better mobile positioning? In the context of quality requirements, decision making typically combines market considerations and design issues in activities such as roadmapping, release planning, and platform scoping. Models that address requirements prioritization in a market-driven context often emphasize functional aspects. (For a comparison of other relevant techniques with Quper, see the sidebar.) Quper provides concepts for reasoning about quality in relation to cost and value and can be used in combination with existing prioritization approaches.

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation

Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further increased bitrates. While LTE Rel-10 supports simultaneous reception of two carriers either in contiguous intra-band or in inter-band CA configuration, the upcoming LTE Rel-11 will add support for non-contiguous (NC) carriers within bands. Supporting NC CA in handsets is a demanding challenge for several reasons. Foremost, the total bandwidth spanned by the carriers may be several times the bandwidth of the individual carriers, possibly spanning an entire band with interfering signals between desired carriers. Furthermore, the distance between TX and RX carriers will vary and worse, may be much smaller than the fixed duplex distance for LTE Rel-8 and W-CDMA single carrier operation [2-5].

Introducing Support for Release Planning of Quality Requirements — An Industrial Evaluation of the QUPER Model

In market-driven product development and release planning, it is important to market success to find the right balance among competing quality requirements. To address this issue, a conceptual model that incorporates quality as a dimension in addition to the cost and value dimensions used in prioritisation approaches for functional requirements has been developed. In this paper, we present an industrial evaluation of the model. The results indicate that the quality performance model provides helpful information about quality requirements in release planning. All subjects stated that the most difficult estimations may be more accurate by using the quality performance model.

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers that represent thermometer-coded oversampled sinusoidal LO waveforms. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm2, draws 26 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

This paper presents an architecture of an autocorrelator for Orthogonal Frequency Division Multiplexing systems. The received signal is quantized to only the sign-bit, which dramatically simplifies the frequency offset estimation. Hardware cost is reduced under the assumption that synchronization during acquisition does not have to be very accurate, but sufficient for coarse estimation. The architecture is synthesized towards a 65nm low-leakage high threshold standard cell CMOS library. The proposed architecture results in area reduction of 93% if compared to typical 8-bit implementation. The area occupied by the architecture is 0.063 mm2. The architecture is evaluated for WLAN, LTE and DVB-H. Power simulations for DVB-H transmission shows a power consumption of 4.8µW per symbol.

Performance Analysis of Sign-Based Pre-FFT Synchronization in OFDM Systems

This paper treats the feasibility to use only the sign bit of the in-phase and quadrature components when estimating time and frequency in OFDM systems. Using only the sign bit is shown to result in a frequency dependent bias, which can be easily compensated. The approach is evaluated for LTE and DVB-H, when the estimation is performed using the cyclic prefix, and for WLAN 802.11g, when the estimation is done using the short training field (STF). The performance is compared to a floating point implementation, and it is also compared to what is believed to be reasonable requirements for initial time and frequency estimation.

A reconfigurable OFDM inner receiver implemented in the CAL dataflow language

This paper presents a reconfigurable inner receiver for the LTE, DVB-H, and IEEE802.11n (WLAN) radio systems, all of which are based on orthogonal frequency division multiplexing (OFDM). The receiver is implemented in the CAL language. An FPGA-based hardware implementation is synthesized from RTL generated from the CAL description. The purpose of our work is to investigate the feasibility of dataflow methodology for high-level description of digital radio transceivers.

Analysis of a novel low complex SNR estimation technique for OFDM systems

Signal-to-noise ratio (SNR) estimation is commonly used in wireless receivers to enhance the performance in different ways. In this paper a novel low complexity SNR estimator for OFDM is proposed. The estimator might be implemented using floating point representation or by using only the sign-bit, and can if desired be effectively implemented by reconfiguring the standard correlator used for time- and frequency estimation. Closed form expressions for the SNR estimate are derived for both the floating point implementation and the sign-bit implementation, and compared to simulation results both for an additive white Gaussian noise (AWGN) channel and for a frequency selective channel showing the feasibility of the proposed algorithm.

A 4.75–34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS

A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75-34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.