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Dive into the research topics where Poonacha Kongetira is active.

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Featured researches published by Poonacha Kongetira.


Journal of Vacuum Science & Technology B | 1997

Expression for the growth rate of selective epitaxial growth of silicon using dichlorosilane, hydrogen chloride, and hydrogen in a low pressure chemical vapor deposition pancake reactor

Poonacha Kongetira; Gerold W. Neudeck; Christos G. Takoudis

A semiempirical expression was developed for the growth rate of selective epitaxial growth (SEG) and epitaxial lateral overgrowth of silicon in a rf heated cold-wall low pressure chemical vapor deposition pancake reactor for the dichlorosilane-HCl–H2 system. The model was obtained for temperatures ranging from 920 to 1020 °C, system pressures from 40 to 150 Torr, and over a range of HCl and dichlorosilane gas flows. The growth rate expression is the sum of a growth term which is a function of the partial pressures of dichlorosilane (SiCl2H2) and hydrogen, and an etch term that varies with the partial pressure of HCl. The growth and etch terms have a temperature Arrhenius relation with activation energies of Egr=2.266 and Eet=1.349 eV, respectively. Included is a term to account for the SEG growth rate dependence on the ratio of SiO2 area coverage to silicon wafer area. A methodology was developed for obtaining the coefficients for the semiempirical growth rate expression from several sets of experiments.


Archive | 1997

Single ended match sense amplifier

Poonacha Kongetira


Archive | 1997

Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals

Poonacha Kongetira


Archive | 2004

Efficient method of data transfer between register files and memories

Shree Kant; Kenway Tam; Poonacha Kongetira; Yuang-jung D. Lin; Zhen W. Liu; Kathirgamar Aingaran


Archive | 2001

Superscalar processor having content addressable memory structures for determining dependencies

Micah C. Knapp; Poonacha Kongetira; Marc E. Lamere; Julie M. Staraitis


Archive | 2002

Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution

Daniel Leibholz; Poonacha Kongetira


Archive | 2002

Fast instruction dependency multiplexer

Karthik Balakrishnan; Poonacha Kongetira; Sanjay Patel; Ketaki Rao


Archive | 2000

Instruction dependency scoreboard with a hierarchical structure

Richard H. Larson; Sanjay Patel; Poonacha Kongetira; Daniel Leibholz


情報処理 | 2005

1. Niagara: 32ウェイマルチスレッドSPARCプロセッサ(実例, 新世代マイクロプロセッサアーキテクチャ(後編))

Poonacha Kongetira; Kathirgamar Aingaran; Kunle Olukotun; 修一 坂井; 正裕 五島


IPSJ Magazine | 2005

New Generation Microprocessor Architecture (2):NIAGARA: A 32-Way Multithreaded SPARC Processor

Poonacha Kongetira; Kathirgamar Aingaran; Kunle Olukotun; Shuichi Sakai; Masahiro Goshima

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Christos G. Takoudis

University of Illinois at Chicago

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