Gerold W. Neudeck

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.

Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth

We report a resonant cavity Si photodiode grown by merged epitaxial lateral overgrowth. At a reverse bias of 5 V, the dark current was 2.7 pA and the bandwidth exceeded 34 GHz. The peak quantum efficiencies ranged from 42% at 704 nm to 31% at 836 nm. This is the highest speed reported for a Si p-i-n photodiode and the highest bandwidth-efficiency product for any Si-based photodetector.

Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm/spl times/150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 /spl mu/m/spl times/500 /spl mu/m) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFETs were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA//spl mu/m, and a subthreshold swing of 76 mV/dec was measured.

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V/sub G/-V/sub T/ values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range.<<ETX>>

On the design of piezoresistive silicon cantilevers with stress concentration regions for scanning probe microscopy applications

In this paper, the design of silicon based cantilevers for scanning probe microscopy has been described in detail. ANSYS software has been used as a tool to design and model the mechanical properties of the silicon based cantilevers. The incorporation of stress concentration regions (SCRs) with a thickness smaller than the cantilever thickness, to localize stresses, has been explored in detail to enhance the piezoresistive displacement, force, and torque sensitivity. In addition, SCRs of widths less than the cantilever width have also been explored. Two basic designs were studied, i.e. a rectangular cantilever and a U-shaped cantilever. The placement of the SCR was found to be critical, and optimal placement and thickness of the SCR can result in a 2× and 5× improvement in piezoresistive displacement and force sensitivity, respectively, for the rectangular cantilever. For the U-shaped cantilever, the torsional piezoresistive sensitivity was found to increase by 5×, depending on the SCR thickness. Process flows and associated fabrication challenges for the proposed cantilever structures are also presented.

Confined lateral selective epitaxial growth of silicon for device fabrication

An epitaxy technique, confined lateral selective epitaxial growth (CLSEG), which produces wide, thin slabs of single-crystal silicon over insulator, using only conventional processing, is discussed. As-grown films of CLSEG 0.9 mu m thick, 8.0 mu m wide, and 500 mu m long were produced at 1000 degrees C at reduced pressure. Junction diodes fabricated in CLSEG material show ideality factors of 1.05 with reverse leakage currents comparable to those of diodes built in SEG homoepitaxial material. Metal-gate p-channel MOSFETs in CLSEG with channel dopings of 2*10/sup 16/ cm/sup -3/ exhibit average mobilities of 283 cm/sup 2//V-s and subthreshold slopes of 223 mV/decade.<<ETX>>

Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth

Three-dimensionally integrated silicon-on-insulator MOS transistors built employing localized silicon epitaxy are discussed. Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated. >

An amorphous silicon thin film transistor: Theory and experiment☆

Abstract The volt-ampere characteristics for a thin film transistor fabricated with vacuum deposited amorphous silicon as the semiconductor is presented. The substrate is single crystalline silicon with a 3000 A layer of thermally grown silicon dioxide as the insulator. The gate is a buried N+ phosphorus diffused region while the source and drain contacts are interdigited fingers of aluminum. By using the Cohen-Fritzsche-Ovshinsky model for the density of localized states in the mobility gap, the VG vs ID characteristic at small values of VD is predicted and experimentally verified. This characteristic is used to theoretically predict the family of ID curves for the TFT over a range of VG and VD. The theory and experiment agree exceptionally well below the gate-drain pinch-off, thereby verifying the theory of a TFT with a uniform distribution of traps in the band-gap.

Selective epitaxial growth silicon bipolar transistors for material characterization

In development of the epitaxial lateral overgrowth (ELO) bipolar transistor, devices were fabricated in silicon selective epitaxial growth (SEG). These devices were used to electrically characterize the quality of the SEG material. Three silicon bipolar transistors, with almost identical doping profiles and geometries were simultaneously fabricated on the same wafer and their electrical characteristics compared. The three transistors were located in the substrate, a single SEG layer, and a double (interrupted growth) SEG layer. The SEG silicon was grown in a reduced-pressure RF-heated pancake-type epitaxial reactor at 950 degrees C and 150 torr. The transistors were tested for junction ideality factors, junction reverse-bias leakage currents, and forward DC current gain. Test results indicated the excellent device quality of the SEG material relative to the substrate. >