Poras T. Balsara

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

Phase-domain all-digital phase-locked loop

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 0.13-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs. The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications. In this paper, we present the mathematical description and operational details of the phase-domain ADPLL.

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed /spl Sigma//spl Delta/ dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is -112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below -62 dBc, while the far-out spurs are below -80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

Matrix inversion and triangularization problems are common to a wide variety of communication systems, signal processing applications and solution of a set of linear equations. Matrix inversion is a computationally intensive process and its hardware implementation based on fixed-point (FP) arithmetic is a challenging problem. This paper proposes a fully parallel VLSI architecture under fixed-precision for the inverse computation of a real square matrix using QR decomposition with modified Gram-Schmidt (MGS) orthogonalization. The MGS algorithm is stable and accurate to the integral multiples of machine precision under fixed-precision for a well-conditioned non-singular matrix. For typical matrices (4 times 4) found in MIMO communication systems, the proposed architecture was able to achieve a clock rate of 277 MHz with a latency of 18 time units and area of 72K gates using 0.18-mum CMOS technology. For a generic square matrix of order n, the latency required is 5n - 2 which is better than all previously known architectures. With the use of LUTs and log-domain computations, the total area has been reduced compared to architectures based on linear-domain computations

Event-driven Simulation and modeling of phase noise of an RF oscillator

A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique.

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS

All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS

An all-digital frequency synthesizer for a single-chip Bluetooth radio is fabricated in 0.13/spl mu/m CMOS, and operates in a digitally-synchronous phase domain that naturally incorporates wideband GFSK modulation. The synthesizer includes a pulse-shaping TX filter and near class-E PA with digital amplitude control. Close-in phase noise is -86.2dBc/Hz, integrated rms phase noise is 0.9/spl deg/, and settling time is /spl les/ 50/spl mu/s.