Sujan K. Manohar

94.6% peak efficiency DCM buck converter with fast adaptive dead-time control

This paper presents a dynamic logic based adaptive dead-time control circuit (DADTC) for fast and adaptive control to minimize body diode conduction losses and dead-time of the buck regulator operating in discontinuous conduction mode (DCM). Dead-time is an important metric for improving efficiency of low voltage converters. DADTC provides instant sensing and feedback based on the load to minimize dead-time significantly compared to prior art and enables higher overall power efficiency of the converter. Further, the presented buck converter has inherent pulse skipping mode to lower the switching frequency at light loads further enhancing light load efficiency. The buck regulator was fabricated in 0.35 μm CMOS process with an input voltage range of 1.8V-3V and load current range of 1mA-200mA. Measurement results show that the proposed design achieves peak power efficiency of 94.6% and a high overall power efficiency ( > ~89%) for load currents greater than 5mA with a sensing delay of only ~5ns for VIN = 1.8V.

Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency

Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip DC-DC converters. As a feasibility study of using NEMS in integrated power electronics, discontinuous conduction mode (DCM) buck regulator with specifications suitable for portable applications has been implemented in a NEMS-CMOS hybrid design and the results are compared against a standard commercial 0.35 μm CMOS implementation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5-10nm. This work shows that NEMS-CMOS hybrid DC-DC converter has an area savings of 60V over CMOS and achieves 95% efficiency at max load condition (50mA).

Ultra low power high efficiency charge pump design using NEM relays

The zero leakage operation of Nano-electromechanical (NEM) relays make the device a promising candidate among emerging devices. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip power management circuits. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5 – 10nm. As a feasibility study of using NEMS in integrated power electronics, a step-down charge pump with specifications suitable for audio power amplifier applications has been implemented and the results are compared against a standard commercial 65nm CMOS implementation. This work shows that NEM relay based charge pump has an area savings of 73X, power savings of 14X over CMOS and achieves 96:1% efficiency at max load condition (18mA).

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management

Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SS-WVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN <; VDD or VDDIN >; VDD) in any step size (paper shows 25mv step) with no requirement for special low-Vτ or high-Vτ devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.

The sustainability of new technologies in vehicular transportation

This paper compares the sustainability of three new technologies in vehicular transportation which consist of (1) innovations in the fuel the vehicles use and (2) innovations in the vehicle design itself. An array of vehicle platforms, which consist of different vehicle designs and fuels types, are modeled and a life cycle analysis (LCA) is performed to find the total energy consumption and emissions of each model. As high energy consumption and pollution become growing concerns, this paper aims to provide a better understanding of where new advancements in vehicular technology should be focused.

Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop

The zero leakage operation of Nano-electromechanical (NEM) relays has generated a lot of interest in low power logic design. Mechanical delay of the switches is orders of magnitude larger than the electrical delay and hence limits the speed of operation of NEM based digital logic circuits. The mechanical delay is inversely proportional to the gate-base voltage (Vgb). This paper presents an integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb. The parallel plate capacitance between the gate and base of the relay is used to realize the storage capacitor for the doubler. It has been shown that for a flop fanout of 1, 2X performance boost could be achieved with 2X increase in area and 0.5X increase in power. For larger fanouts, the doubler is shared across multiple flops minimizing the area overhead. This approach can be extended as long as the overdrive does not create any reliability issues in the device. Accurate Verilog-A models were developed based on published fabrication results of scaled NEM relays [1] operating at 1V with a nominal air gap of 5 – 10nm. The area, power and performance trade-off for a sequential logic circuit with and without charge boosting is presented.

NEM relay based memory architectures for low power design

Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. This work proposes three new NEM relay based parallel readout memory bitcell architectures that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. Accurate Verilog-A models were developed based on published fabrication results of NEM relays operating at 1V with a nominal air gap of 5 - 10nm. Bitcell stability and access time analysis are performed for all the proposed architectures and the results are presented.

Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in , and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique , to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V-13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps.

Automated G m C filter design: A case study in accelerated reuse of analog circuit design

The increasing complexity of analog design for SoCs has become a bottleneck due to the lack of established design automation flows. Consequently, reuse of analog design IP (intellectual property) is becoming increasingly prevalent in the semiconductor industry. Traditional design reuse approaches still require a considerable amount of a designers time for a new set of specifications or migration to new technology nodes. This paper describes an accelerated design reuse strategy for analog circuit design using design automation techniques. As a case study, we developed an automated GmC filter design flow using a combination of heuristic and stochastic optimization methods. The resultant IP is capable of generating SPICE netlists for wide sets of specifications and different technology nodes with minimal designer effort.

Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency

In CMOS switches, the input signal modulates the on-channel resistance for a constant gate voltage. This necessitates over design of CMOS switches. Also, further CMOS scaling in the nanometer regime has failed to improve energy efficiency due to increasing leakage energy. Looking beyond CMOS, nanoelectromechanical (NEM) relays are a promising class of emerging devices that exhibit energy-efficient switching and zero leakage operation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Numerous end applications of NEM relay logic circuits have been proposed recently, including digital logic and memory. NEMS-based miniature switches form an interesting alternative in power management integrated circuits, the area of which is primarily dominated by CMOS power transistors. This study explores discontinuous-conduction mode buck regulator with specifications suitable for portable applications using a NEMS-CMOS hybrid design, and the results are compared against a standard commercial 0.35-μm CMOS implementation. The electromechanical model has been developed for a suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm published in the literature. The model accounts for the mechanical, electrical, and dispersion effects in the relay. This study shows that NEMS-CMOS hybrid dc-dc converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100 mA.