Pramod Govindan

Processing algorithms for three-dimensional data compression of ultrasonic radio frequency signals

Ultrasonic systems are widely used in imaging applications for non-destructive evaluation, quality assurance and medical diagnosis. These applications require large volumes of data to be processed, stored and/or transmitted in real-time. Therefore it is essential to compress the acquired ultrasonic radio frequency (RF) signal without inadvertently degrading desirable signal features. In this paper, two algorithms for ultrasonic signal compression are analysed based on: sub-band elimination using discrete wavelet transform; and decimation/interpolation using time-shift property of Fourier transform. Both algorithms offer high signal reconstruction quality with a peak signal-to-noise ratio (PSNR) between 36 to 39 dB for minimum 80% compression. The computational loads and signal reconstruction quality are examined in order to determine the best compression method in terms of the choice of DWT kernel, sub-band decomposition architecture and computational efficiency. Furthermore, for compressing a large amount of volumetric information, three-dimensional (3D) compression algorithms are designed by utilising the temporal and spatial correlation properties of the ultrasonic RF signals. The performance analysis indicates that the 3D compression algorithm presented in this paper offers an overall 3D compression ratio of 95% with a minimum PSNR of 27 dB.

Hardware and software architectures for computationally efficient three-dimensional ultrasonic data compression

Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for real-time ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

3D ultrasonic signal compression algorithms for high signal fidelity

Ultrasonic signal processing applications require huge amounts of data to be processed. Further, high computational performance is essential to meet the real-time requirements. Compression of the signal helps to reduce the data size and storage requirements as well as allow for rapid transmission of data to remote locations. High signal fidelity is significant in many of practical applications like ultrasound medical imaging and nondestructive testing. In this study, we discuss two methods for ultrasonic signal compression which offer high signal fidelity - Discrete Wavelet Transform and signal decimation with the Nyquist rate limit. The compression algorithm is implemented on a reconfigurable system-on-chip platform using programmable hardware logic as well as in software using an embedded processor. The implementation details and the performance of the compression algorithms on both the hardware and software are analyzed in this paper.

Performance evaluation of FPGA based embedded ARM processor for ultrasonic imaging

This study evaluates the performance of an FPGA based embedded ARM processor system to implement signal processing for ultrasonic imaging and nondestructive testing applications. FPGA based embedded processors possess many advantages including a reduced overall development time, increased performance, and the ability to perform hardware-software (HW/SW) co-design. This study examines the execution performance of split spectrum processing, chirplet signal decomposition, Wigner-Ville distributions and short time Fourier transform implementations, on two embedded processing platforms: a Xilinx Virtex-5 FPGA with embedded MicroBlaze processor and a Xilinx Zynq FPGA with embedded ARM processor. Overall, the Xilinx Zynq FPGA significantly outperforms the Virtex-5 based system in software applications.

Performance evaluation of 3D compression for ultrasonic nondestructive testing applications

Ultrasonic imaging and nondestructive testing applications require large volumes of data. Therefore, it is essential to compress data for storage and transmission without degrading the signal quality or inadvertently damaging desirable signal features. In this study, the ultrasonic signal compression and signal reconstruction is implemented using discrete wavelet transform (DWT), and direct signal decimation and reconstruction by interpolation when sampling rate exceeds several folds above the Nyquist rate. The objective of this study is to design 1D and 3D compressions and evaluate the degree of compression of ultrasonic data as a function of data integrity. The compression performance is evaluated by calculating the PSNR (peak SNR) and the correlation between the original and reconstructed signals with respect to compression ratio. The performance of the 3D compression algorithm used in this study offers an overall 3D compression ratio of 95% with a PSNR of 27dB indicating high signal fidelity.

Reconfigurable and programmable System-On-Chip hardware platform for real-time ultrasonic testing applications

Present day ultrasonic signal processing applications such as medical imaging and non-destructive testing has stringent requirements on low cost and portability to provide high quality diagnostics and characterization at real-time pace. Advancements in the field of digital signal processing, embedded computing, and semiconductor technologies, have significantly assisted ultrasound researchers in the development of low-cost, portable, and computationally efficient systems. In this study, a reconfigurable and programmable ultrasonic testing system (RPUTS) is designed and developed to effortlessly test and evaluate a wide variety of ultrasonic signal processing applications. RPUTS integrates a reconfigurable Analog Front-End (AFE) which supports up to 8 transducers suitable for phased-array implementations. The back-end processing is provided by Xilinx Zynq System-on-Chip (SoC) which includes a powerful embedded ARM processor. Zynq SoC manages the overall system configuration as well as the execution of the signal processing algorithms. This study demonstrates the capabilities of RPUTS by realizing a complete ultrasonic testing system which acquires ultrasonic data and performs high-speed 3D compression on the acquired data at real-time rate.

Dynamically reconfigurable analog front-end for ultrasonic imaging applications

With extensive applications in imaging and material evaluation, ultrasonic systems have evolved over decades to efficient and more sophisticated equipment. These systems are built aiming at a specific application or at specific target material. In order to make these systems portable and adaptable to the testing environment, we focus on building a more flexible and programmable hardware. We present a fully configurable Analog Front-End (AFE) which possesses the capability for dynamic re-configuration by using an ARM Core for real-time control, data acquisition and signal analysis. The flexibility built into the AFE facilitates various beamforming and signal conditioning requirements. This arrangement enables the back-end processor to support various signal processing algorithms.

Hardware-software co-design of 3D data compression for real-time ultrasonic imaging applications

Many of the ultrasonic NDE and imaging applications require processing of huge amount of data in real-time. Compression of acquired data helps to reduce the storage and to rapidly transmit information to remote locations for further analysis. Signal fidelity, computational speed and resource utilization are the major parameters to be considered while designing the architecture for the compression algorithm. The objective of this study is to implement discrete wavelet transform (DWT) based ultrasonic 3D data compression algorithm on a reconfigurable ultrasonic system-on-chip hardware platform targeted for real-time ultrasonic imaging applications. The reconfigurable platform allows analysis of multiple architectures to suit various applications. The algorithm is implemented as a hardware-only design and hardware-software co-design. Both implementations provide a high signal compression ratio of about 98% with good quality signal reconstruction. This study demonstrates that, compressing 33 MBytes of experimental ultrasonic 3D data into 0.4 MBytes requires only one-fourth of a second for hardware-only design, and one minute for hardware-software co-design, making both designs highly suitable for real-time ultrasonic imaging applications.

Programmable analog front-end system for ultrasonic SoC hardware

This study presents a scheme for enhancing the capabilities of an ultrasonic hardware platform leading to a fully reconfigurable system allowing for dynamic control over the analog front-end. This system presents a robust approach for nondestructive testing, data analysis and imaging applications. The fully programmable analog front-end system proposed in this paper supports up to 8 ultrasonic sensors. The components of this system are dynamically configurable by a Zynq system-on-chip (SoC) module for real-time ultrasonic data acquisition and analysis. This reconfigurable system enables ultrasonic researchers to efficiently prototype different experiments and to incorporate high performance ultrasonic signal and image processing algorithms.

Architecture of the reconfigurable ultrasonic system-on-chip hardware platform

Design of ultrasonic signal processing systems requires a paradigm shift to fully utilise the benefits of recent advancements in the field of integrated circuits. It is necessary to design a standardised common platform that provides the flexibility to develop both software and hardware solutions. This enables the user to explore the full design space including software only, hardware only, and hardware/software co-design. To fulfil this purpose, the authors introduce the reconfigurable ultrasonic system-on-chip hardware (RUSH) platform. RUSH provides a common basis which significantly reduces the effort required to develop an ultrasonic signal processing system able to process the full range of ultrasound from 20 kHz to 20 MHz. Furthermore, this study aims to make the design and implementation of signal processing algorithms in embedded software and reconfigurable hardware very efficient. To demonstrate the computational efficiency and design flexibility of the RUSH platform, several important computationally intense algorithms such as split spectrum processing, chirplet signal decomposition and coherent averaging have been successfully ported to the RUSH platform, emphasising the many parts of the RUSH architecture.