Pranav Garg

The Nanoscale Silicon Accumulation-Mode MOSFET—A Comprehensive Numerical Study

Recently, we proposed and experimentally demonstrated a very simply structured unipolar accumulation-type field- effect transistor (FET) using silicon nanowires (NWs). In this paper, we present an extensive numerical study of this accumulation metal-oxide-semiconductor FET (AMOSFET). This single-doping-type ohmically contacted structure relies on having a nanoscale dimension normal to the gate, thereby forcing the current path through an accumulated (ON-state) or depleted (OFF-state) region. It also relies on having contact-barrier and doping-dependent minimum source and drain lengths as well as minimum gate lengths to insure unipolar transistor action. The comprehensive report presented extends our previous examination of the devices operation by using extensive numerical simulations to offer a greater understanding of the origins of transistor operation. We explore a wide range of structural and material parameters to study their effects on the linear, saturation, and OFF-state currents. We also delve deeper into the uniquely weak dependence on gate capacitance. This paper establishes that this extremely simple accumulation-mode transistor structure offers its best performance for the more highly doped thinnest devices, giving, for example, for a 1017-cm-3 (doping) and 20-nm device a leakage current of ~40-17 A/mum, a subthreshold swing of 65 mV/dec, and an on-off ratio approximately 1010. This paper also shows that such results should be attainable for AMOSFETs fabricated using NWs and nanoribbons, as well as nanoscale thin-film materials.

Step-and-Grow Approach for Precisely Positioned Nanowire Array Structure Fabrication

A novel fabrication approach for forming precisely positioned nanowire array structures is introduced. The approach is suitable for potentially economical and environmentally safe manufacturing. For the demonstration of this approach, 100nm wide Sn nanowires and 150nm wide polyaniline (PANI) nanowires were synthesized using an electro-chemical deposition technique and a process we term the step-and-grow method. The nanowires produced exhibit the expected properties. For example, synthesized PANI nanowires showed reasonable ranges of electrical conductivities (e.g., 25S/cm for a 200nm wide, 200nm high, 10um long nanowire), and formed ohmic contact with electrodes on a substrate. It is shown that the polydimethylsiloxane (PDMS) stepping template mold used for our step-and-grow nanowire synthesis process can be used at least up to 40 times without degradation.Copyright