Stephen J. Fonash

Crystallized Si films by low‐temperature rapid thermal annealing of amorphous silicon

Low‐temperature rapid thermal annealing has been used to crystallize both undoped and doped amorphous silicon (a‐Si) films deposited at low temperatures. The polycrystalline films produced are completely crystallized with time temperature budgets such as 4 min at 700 °C. Unlike deposited polycrystalline Si films, the grain size in these crystallized films is not limited by film thickness. In the case of undoped a‐Si films crystallized by this approach, the resulting conductivity is comparable to that achieved in undoped polycrystalline Si films produced by much higher processing temperatures. In the case of doped a‐Si films, the resulting crystallized film yields a conductivity of 160 S/cm, a value which is comparable to the highest reported for doped polycrystalline and microcrystalline silicon. These doped films are found to have mobility values of ∼13 cm2/V s.

Polycrystalline silicon thin film transistors on Corning 7059 glass substrates using short time, low‐temperature processing

A new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported. This unique fabrication process has the advantages of short processing time and low processing temperature (≤600 °C). The processing is based on the key step of using an ultrathin Pd layer, introduced to the surface of the glass prior to the deposition of an a‐Si:H film, to reduce the crystallization time and temperature. It is also based on using an electron cyclotron resonance hydrogen plasma to reduced the passivation time. The n‐channel TFTs produced by this new fabrication process have mobilities of 20 cm2/V s, and off‐currents of 0.5 pA/μm.

Selective area crystallization of amorphous silicon films by low‐temperature rapid thermal annealing

We report the first demonstration of selective area crystallization of amorphous silicon films using low‐temperature rapid thermal annealing. Crystallization temperatures as low as 500 °C were achieved with the help of a thermally evaporated ultrathin metal layer. The selective area crystallization was accomplished by using this ultrathin metal layer to define the region to be crystallized. The edge between two regions, that which has been crystallized and that which has not, is found to be very sharp.

The role of the interfacial layer in metal−semiconductor solar cells

Recent work has been reported on metal−semiconductor (Schottky barrier) solar cells in which efficiencies comparable to silicon p−n devices have been achieved. In these devices, the interfacial layer is believed to play an important role. In this discussion the nature of that role is examined. It is shown that the interfacial layer can enhance performance, and an outline for optimizing that enhancement is presented. The results are presented assuming n−type semiconductor material; however, the conclusions are equally valid for structures using p−type material.

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.

Range of validity of the surface‐photovoltage diffusion length measurement: A computer simulation

The surface‐photovoltage diffusion length measurement is analyzed in depth to determine its range of applicability and cause of failure when it no longer yields the diffusion length. It is shown that this technique is generally not valid for amorphous materials, but is highly useful for crystalline semiconductors. The problem of applicability of the surface‐photovoltage diffusion length measurement to amorphous materials is not alleviated by using thicker samples or by using chopped light illumination through the back. It is determined that the validity of the surface‐photovoltage method requires a density of midgap states <1013 cm−3 eV−1.

Low temperature selective crystallization of amorphous silicon

Abstract We have used rapid thermal annealing to crystallize PECVD a-Si:H films deposited on glass at low thermal budgets of 700°C/4 min. The a-Si:H films can be selectively crystallized using thermal budgets lower than 700°C/4min. by selectively depositing an ultrathin Pd layer on the silicon surface. We have investigated the electrical and the structural properties of these selectively crystallized films.

A reevaluation of the meaning of capacitance plots for Schottky‐barrier‐type diodes

Capacitance–voltage (C‐V) data, in the form of 1/C2 versus voltage plots, have long been used to extract information on the space charge region doping and barrier height in Schottky‐barrier‐type diodes. The meaning of the slope and voltage intercept of these 1/C2 versus voltage plots for reverse‐biased diodes is reexamined in this analysis for the case when there is an inadvertent or purposeful interface layer present. The possibility of having interface states, one type of which communicates with the metal and another type of which communicates with the semiconductor, is considered, as is the fact that these two classes of states may, or may not, be able to follow an ac signal. The analysis first assumes that the densities of these states do not vary across the gap; this restriction is later relaxed and the possibility of variable densities of interface states is considered. The results of the analysis differ from those of previous studies. In general, it is found that most sets of interface state charac...

Effect of ion‐beam sputter damage on Schottky barrier formation in silicon

Abnormal rectifying behavior has been observed in molybdenum/silicon Schottky barrier diodes produced by ion‐beam sputter deposition of Mo on single‐crystal Si. Rectifying, rather than ohmic contacts are obtained on p‐type Si, while ohmic behavior is seen on n‐type Si. These results are contrary to the usual results reported in the literature, and are shown to be caused by ion‐beam surface damage of Si. The damage does not simply cause a surface layer of high‐recombination velocity, but rather tends to bend the Si band edges downwards, irrespective of the Si conductivity type.

Computer analysis of the role of p -layer quality, thickness, transport mechanisms, and contact barrier height in the performance of hydrogenated amorphous silicon p - i - n solar cells

The transport simulations provided by the computer program AMPS have been used to give an in‐depth analysis of the role of the p‐layer contact barrier height, contact transport mechanism, p‐layer thickness, and p‐layer quality on the performance of hydrogenated amorphous silicon p‐i‐n solar cells. We demonstrate for the first time that, if the contact barrier height to the p‐layer is below a critical value and if tunneling through the p‐layer is not important, then the performance of cells with either active or dead p‐layers varies with contact barrier height regardless of p‐layer thickness. We show that, even for an optimistic p‐layer active doping density of 1019 cm−3, this critical barrier height is high (∼1.2 eV). Our analysis implies that one of two situations must occur in an actual a‐Si:H p‐i‐n structure: the p‐layer contact plays an important role in determining cell efficiency, or the tunneling of holes through the front contact/p‐layer interface must be important. Comparison of simulated results...