Prasad N. Golla

A simple and fast parallel round-robin arbiter for high-speed switch control and scheduling

The design of a fast and fair arbiter is critical to the efficiency of the scheduling algorithm, which is the key to the performance of a high-speed packet switch. In this paper, we propose a parallel round-robin arbiter (PRRA) design, based on a binary-tree structure. We show that our design is simpler and faster than existing round-robin arbiter designs.

Impact of polarized traffic on scheduling algorithms for high-speed optical switches

The problem of maintaining high throughput of a slotted switch matrix while observing data transit time limits involves balancing two contradictory requirements. It is desired to transmit only full packets through the matrix whenever possible, even when traffic is unevenly distributed among the input queues. However, to prevent loss of data due to timeout it will be necessary to transmit some incomplete packets from queues that have light traffic. Our scheme for scheduling the switch matrix takes into account the conflicting requirements of data timeout and switch matrix efficiency. Using only elementary queue state information (data content and age), this scheme works by presenting ideal service requests to the central scheduler. The scheduler does not incorporate any priority scheme and can use any of a number of available scheduling algorithms that provide efficient matrix operation and fairness of service for the input data queues. Simulations of a switch system using our scheme demonstrate that polarized (unevenly distributed) traffic can be handled with a loss of only a few percent of the switch matrix capacity.

QoS mechanism for prioritized flow-control for network elements handling high-speed traffic

Handling of QoS priorities to differentiate flows is critical in the next generation Internet with ever increasing traffic. We present a scheme called p-persistent binary tree arbiter (PBTA) that approximates the general processor sharing (GPS) model. PBTA arbitrates between contending flows based on various quality of service parameters which are mapped to their weights or priorities; and, by being stateful, it provides a fair arbitration among the contending flows across the individual timeslots. Our simulations show that PBTA provides a fair technique among the flows by providing the proper service ratios and transit times conforming to the appropriate traffic classes. The advantage of the scheme is that it requires no modifications to the other scheduling algorithms. The preliminary FPGA implementation shows that the mechanism is implementable, fast, and conservative in chip area.

Multiserver switch scheduling for high speed optical switches

A switch matrix implemented as an optical crossbar using semiconductor optical amplifiers is able to accommodate extreme concentrations of data traffic. Due to the need to reduce optical guard band overhead it is beneficial to switch fixed size bursts of data cells on a time slot basis. The high capacity of the optical matrix supports multiple optical ports per burst card, and the implementation of multiple queue servers per burst card helps make better use of the multiplicity of ports. Problems associated with arbitrating multiple ports and multiple servers per burst card have been resolved by extending the operation of existing iterative, single server scheduling algorithms. The multiserver arbitration time will be in proportion to the number of servers -- corresponding to the channels of DWDM link -- unless a reconciliation stage is used after each iteration when an arbiter per server is used. The reconciliation stage sets the problem of broken data dependencies between server arbitrations in this case. Further, to address the time limitations for computing the scheduling solution, parallel arbiter implementations have been developed and tested against single arbiter designs. Again, the broken dependencies between iterations of an arbitration are addressed through the use of a grant reconciliation stage. The use of multiple queue servers per burst card also resolves some of the data loss problems related to polarized traffic. Simulations of the multiple server and parallel arbiter implementations have demonstrated their efficiency compared to previous implementations. Compounded to this problem is maintaining high throughput of the switch matrix while observing data transit time limits. This involves balancing two contradictory requirements; switch or line card efficiency and data transit times. To improve efficiency it is desirable to transmit only full packets. However, to prevent loss of data due to timeout it will be necessary to transmit some incomplete packets. We investigate three approaches -- thrifty, conservative, and greedy request policies. Using data content and age we demonstrate that unevenly distributed traffic can be handled better with multiserver switching matrices.

Multi-server scheduling for high speed optical switches

High performance switching systems of the future employs optical switching matrices to provide the required speed and capacity at competitive costs. Optical WDM technologies coupled with the need to. concentrate data flow capacity at the switch matrix interface introduce the requirement for multiple queue servers at each input and output port. Such a multiserver architecture necessitates the development of novel scheduling algorithms. We developed and tested four iterative scheduling algorithms to assess their performance with respect to existing schedulers for mono-server architectures. A problem that arises because of multiservers in iterative scheduling algorithms is the proper matching of servers and grants after each iteration. We show an effective method to solve this problem and show the feasibility of the multiserver schedulers. The performance of these algorithms is comparable to or better than existing implementations. Switch speedup factors of one and two in combination with configurations of one, two, four, eight, and sixteen servers per port are demonstrated.