Prasana Ravindran

Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link

High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual- (4.5 and 20 ) fabrication process.

A high-speed cryogenic SiGe channel combiner IC for large photon-starved SNSPD arrays

In this paper, the design and characterization of a cryogenic eight-channel pixel combiner circuit designed to readout superconducting nanowire single photon detectors (SNSPDs) is presented. The circuit is designed to amplify, digitize, edge detect, and combine the output signals of an array of eight SNSPDs. The design has been enabled by the development of novel large-signal cryogenic HBT simulation models. The circuit has been fabricated and measurement results demonstrate excellent agreement with simulation.

Power-Optimized Temperature-Distributed Digital Data Link

Interfacing superconducting rapid single flux quantum logic with room temperature electronics requires the development of low-power semiconductor circuitry capable of operating at tens of Gb/s while maintaining sufficient signal to noise to achieve acceptable bit-error-rates. Such data-links must operate with sufficiently low power consumption to permit tens to hundreds of parallel channels to coexist in a single cryostat. This requires a careful trade-off between the power and noise performance of the cryogenically cooled digital amplifiers. Previously demonstrated ultra low-power cryogenic-to-room temperature digital data links have been limited to data rates on the order of a few Gb/s. In this paper we demonstrate a temperature distributed amplifier chain optimized for 30 Gb/s data transmission and consuming just 140 microwatts at 4 K.

A SiGe Ka-band cryogenic low-noise amplifier

The design and characterization of a cryogenic silicon germanium integrated circuit amplifier operating at a center frequency of 22 GHz is presented. The packaged amplifier is measured at 15 K and achieves a gain of 25 dB and a noise temperature below 35 K, which is consistent with simulated performance. It is believed that this is the first reporting of a cryogenic silicon germanium low-noise amplifier operating above 10GHz and that the measured results represent the lowest reported noise temperature for any silicon based low-noise amplifier operating at these frequencies.

Cryogenic SiGe integrated circuits for superconducting nanowire single photon detector readout

There is a growing interest in developing systems employing large arrays of SNSPDs. To make such instruments practical, it is desirable to perform signal processing before transporting the detector outputs to room temperature. We present a cryogenic eight-channel pixel combiner circuit designed to amplify, digitize, edge detect, and combine the output signals of an array of eight SNSPDs. The circuit has been fabricated and measurement results agree well with expectation. The paper will conclude with a summary of ongoing work and future directions.

Active quenching: a new approach to the bias and readout of superconducting nanowire single photon detectors (Conference Presentation)

Superconducting nanowire single photon detectors (SNSPDs) have emerged as a leading choice for high performance single photon detectors due to their low timing jitter, high detection efficiency, and low dark count rates. SNSPDs have typically been biased using a passive quenching scheme in which the bias current of the device is shunted through a resistive load to allow for recovery after a detection event. To prevent latching, the shunting resistor must be approximately an order of magnitude smaller than the peak normal domain resistance of the SNSPD. Consequentially, the pulse amplitude (∝IBRL) and recovery time (∝LK/RL) are both negatively impacted. In this talk, we will describe a novel approach to the bias and read-out of SNSPDs based upon active quenching. We will present detailed design considerations for an active quenching architecture and will show that such an approach has the potential to improve count rates while increasing signal swings to the point where external amplification is no longer required. A silicon germanium (SiGe) active-reset chip design has been designed, implemented, and integrated with a NbTiN SNSPD. The procedure for the SiGe chip design will be described and simulation results will be presented. Finally, detailed measurement results of the complete system will be shown and compared to measurements of the same detector when biased and read-out using a standard passive quenching scheme. It will be shown that the active quenching configuration enables a considerable enhancement to the system performance.

Large-Area Arrays of WSi Superconducting Nanowire Single Photon Detectors

We report on a 160 μm × 160 μm free-space-coupled array of WSi superconducting nanowire single-photon detectors (SNSPDs) developed for the ground receiver of a deep-space optical communication system.