Deepnarayan Gupta

Superconductor analog-to-digital converters

Ultrafast switching speed, low power, natural quantization of magnetic flux, quantum accuracy, and low noise of cryogenic superconductor circuits enable fast and accurate data conversion between the analog and digital domains. Based on rapid single-flux quantum (RSFQ) logic, these integrated circuits are capable of achieving performance levels unattainable by any other technology. Two major classes of superconductor analog-to-digital converters (ADCs) are being developed - Nyquist sampling and oversampling converters. Complete systems with digital sampling at rates of /spl sim/20 GHz and above have been demonstrated using low-temperature superconductor device technology. Some ADC components have also been implemented using high-temperature superconductors. Superconductor ADCs have unique applications in true digital-RF communications, broadband instrumentation, and digital sensor readout. Their designs, test results, and future development trends are reviewed.

Superconductor Digital-RF Receiver Systems

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the worlds first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.

Digital Channelizing Radio Frequency Receiver

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency (RF). Such a receiver consists of a wideband analog-to-digital converter (ADC) modulator and multiple digital channelizer units to extract different frequency bands-of-interest within the broad digitized spectrum. The single-bit oversampled data, from either a lowpass delta or bandpass delta-sigma modulator, are applied to one or more channelizers, each comprising digital in-phase and quadrature mixers and a pair of digital decimation filters. We perform channelization in two steps, the first at full ADC sampling clock frequency with rapid single flux quantum (RSFQ) digital circuits and the second at reduced (decimated) clock frequency with commercial field programmable gate array (FPGA) chips at room temperature. We have demonstrated lowpass and bandpass digital receivers by integrating an ADC modulator and a channelizer unit on the same chip at clock frequencies up to 20 GHz. These 1-cm2 single-chip digital-RF receivers contain over 10,000 Josephson junctions. The channelizing receiver approach can be extended to include multiple ADC modulators and multiple channelizer units on a multi-chip module.

Modular, Multi-Function Digital-RF Receiver Systems

Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10 × 10 mm2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5 × 5 mm2 1.1-GHz bandpass ADC chip to perform worlds first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5 × 5 mm2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application.

High-resolution ADC operation up to 19.6 GHz clock frequency

We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC chip uses the phase modulation–demodulation architecture and on-chip digital filtering. The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as well as decimation digital filter, have been redesigned for operation at 20 GHz. Test results of this 6000 Josephson junction 2G ADC chip at clock frequencies up to 19.6 GHz are described. These test results were compared to the results of ADC functional simulation using MATLAB.

A superconductor high-resolution ADC

This paper presents the development of an Analog-to-Digital Converter (ADC) based on a low-temperature superconductor (Nb) chip and room-temperature interface modules for applications in digital receivers for communications, radars, and electronic warfare. The ADC design, MATLAB/sup TM/ simulations, and experimental results of single- and two-tone tests are described.

Cryocooled wideband digital channelizing radio-frequency receiver based on low-pass ADC

We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation–demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4. 5k A cm −2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed.

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

Progress in Design of Improved High Dynamic Range Analog-to-Digital Converters

We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation-demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement.

Integration of cryocooled superconducting analog-to-digital converter and SiGe output amplifier

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.