Prasanna Kumar Sahu

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Nowadays FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This paper studies the impact of H_Fin and W_Fin variations on various performance matrices including static as well as dynamic figures of merit (FOMs). With the help of aspect ratio (W_Fin/H_Fin), the device is branched into three parts, i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (H_Fin) and width (W_Fin) on various performances including the dc as well as ac FOMs. The static or low-frequency performances like threshold voltage (V_th), on current (I_on), off current (I_off ), power dissipation, transconductance (g_m), output conductance (g_d), transconductance generation factor (TGF = g_m /I_D), early voltage (V_EA), gain (A_V), and dynamic or high-frequency performances as gate capacitance (C_gg), cutoff frequency (f_T), output resistance (R₀), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this paper can be of great help to device engineers in designing 3-D devices as per their requirement.

A functional Link Artificial Neural Network for location management in cellular network

Mobility management is one of the major issues in mobile networks to provide an efficient and low-cost service. In this paper, we intend a prediction-based location management scheme for locating a mobile host (MH) or mobile station, which depends on its history of movement pattern of a mobile subscriber. A multilayer neural network (MNN) model for mobile movement prediction is designed to predict the future movement of a mobile host. For predicting the location of a mobile host the MNN is trained with respect to the data obtained from the movement pattern. The difficulties associated with the location management can be solved by nonlinear neural network that is computationally efficient. The major issue in feed forward neural network such as Multilayer perceptron (MLP) trained with back Propagation (BP) is that it requires a large amount of computation time for learning the network. Functional Link Neural Network (FLNN) is proposed here and that is simpler than MLP-BP. This is basically a single layer structure in which nonlinearity is introduced where the input pattern is enhanced with nonlinear functional expansion. The novelty of the proposed work is it requires less computation than that of MLP-BP. With proper choice of functional expansion in case of FLANN, this network performs better than multilayer perceptron with back propagation. It is observed from the simulation result that FLANN outperforms MLP-BP in terms of performance error. It is also shown that proposed network is computationally cheap and gives better classification accuracy than that of MLP classifier.

Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Asymmetric underlap dual-k spacer hybrid fin field-effect transistor (FinFET) is a novel hybrid device that combines three significant and advanced technologies, i.e. ultra-thin body, three-dimensional (3D) FinFET, and asymmetric spacer engineering on a single silicon on insulator platform. This innovative architecture promises to enhance the device performance as compared with conventional FinFET without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects in nanoscale devices. For the first time, this study introduces an asymmetric high-k dielectric spacer near the source side with optimised length in hybrid FinFET and claims an improvement in device integrity. From extensive 3D device simulation, the authors have determined that the proposed architecture is superior in performance as compared with traditional FinFET.

EKF with PSO technique for delineation of P and T wave in electrocardiogram(ECG) signal

The automated detection and delineation of P and T waves in an electrocardiogram (ECG) is a challenging task in biomedical signal processing community, because of its low amplitude, high gradient of noise and lack of universal delineation rule. In this paper, we have investigated the effectiveness of particle swarm optimization (PSO) with extended Kalman filter (EKF) in order to detect and delineate P and T wave in an ECG. PSO is used for selection of optimized parameters which are required to model the ECG signal and also to initialize parameters of EKF. EKF frame work is used to denoise the raw ECG signal and to detect the peak of P and T wave. Finally square operation is used for delineation of P and T wave. Our algorithm has been successfully verified using one realtime ECG database namely QT database.

Analysis of symmetric high-k spacer (SHS) trigate Wavy FinFET: A novel device

This paper evaluates the novelty aspects of symmetric high-k spacer (SHS) trigate wavy FinFET over conventional FinFET. The SHS wavy FinFET is a hybrid device, which combines three significant and advanced technologies i.e., ultrathin body (UTB), Wavy channel FinFET, and high-k spacer on a single silicon on insulator (SOI) platform to enhance the device performance without increasing the chip area. In these recent days, high-k dielectric spacer materials are widely explored because of their better electrostatic control and more immune towards short channel effects (SCEs) in nanoscale devices. For the first time, this paper introduces a symmetric high-k dielectric spacer in Wavy channel FinFET and claims an effective improvement in drive current. In the meantime, the proposed device predicts better performances for analog/RF applications in subthreshold region of operation. From comprehensive 3-D device simulation, we have demonstrated that the proposed device is superior in performance as compared to trigate FinFET.

Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

In this work the sensitivity of process parameters like channel length (L), channel thickness (tSi), and gate work function (M) on various performance metrics of an undoped cylindrical gate all around (GAA) metal-oxide-semiconductor field effect transistor (MOSFET) are systematically analyzed. Undoped GAA MOSFET is a radical invention as it introduces a new direction for transistor scaling. In conventional MOSFET, generally the channel doping concentration is very high to provide high on-state current, but in contrary it causes random dopant fluctuation and threshold voltage variation. So, the undoped nature of GAA MOSFET solves the above complications. Hence, we have analyzed the electrical characteristics as well as the analog/RF performances of undoped GAA MOSFET through Sentaurus device simulator.

A Study of SCEs and Analog FOMs in GS-DG- MOSFET with Lateral Asymmetric Channel Doping

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

Location prediction of mobility management using neural network techniques in cellular network

This work describes the neural network technique to solve location management problem. A multilayer neural model is designed to predict the future prediction of the subscriber based on the past predicted information of the subscriber. In this paper a prediction based location management scheme is proposed for locating a mobile terminal in a communication without losing quality maintain a good response. There are various methods of location management schemes for prediction of the mobile user. Based on individual characteristic of the user, prediction based location management can be implemented. This work is purely analytical which need the past movement of the subscriber. The movement of the mobile target is considered as regular and uniform. An artificial neural network model is used for mobility management to reducing the total cost. Single or multiple mobile targets can be predicted. Among all the neural techniques multilayer perceptron is used for this work. The records is collected from the past movement and is used to train the network for the future prediction. The analytical result of the prediction method is found to be satisfactory.

The performance measure of GS-DG MOSFET: an impact of metal gate work function

The quantitative assessment of the nanoscale gate stack double gate (GS-DG) MOSFET performance values are numerically calculated with different gate metal work functions (Φ m = 4.52 eV, 4.6 eV, 4.7 eV). The effect of electrostatic control on dc, analog and RF figures of merit (FOMs) which includes subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), early voltage (V EA), intrinsic gain (AV), cut off frequency (f T) and transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) have been investigated for the model GS-DG MOSFET. Higher TGF and AV was achieved with Φ m = 4.6 eV for the device. For a better comparison among the analog/RF FOMs, the threshold voltage (V th) is maintained at a constant value for different work function cases. To achieve a constant V th, the channel doping (NA) and source/drain doping (ND) is tuned accordingly for all device cases. Superior f T which is due to higher transconductance (g m) and lower output conductance (g d), was observed for the device. In addition, better gain performances i.e. GFP and GTFP were achieved resulting from improved g m. Thus, the device structure modelled with Φ m of 4.6 eV can be considered as a better candidate for analog and RF circuit applications.

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.