Prashant Dubey

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost

Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increases. Lasers fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, the authors present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio

On Chip Jitter Measurement through a High Accuracy TDC

In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.

Built in Defect Prognosis for Embedded Memories

With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing bitmap diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete bitmap to the tester. The proposed methodology supports testing through a very low cost ATE. This architecture is partitioned to achieve sharing among various memories and at-speed testing.

GALS Based Shared Test Architecture for Embedded Memories

Increasing memory content on SoCs, along with the shrinking technology node (resulting into newer kinds of defects), multiple clocks, and voltage domains necessitate a shared built in self test (BIST) capable of testing memories in different nooks of a chip with least routing congestion and the ability to handle different clock domains. Moreover, the BIST should be programmable so that it can cope up with upcoming defects. Hereby, we propose a shared and programmable BIST architecture based on GALS methodology to cater to the aforesaid needs

Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost

Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increase. Laser fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, we present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio.

Tongue: An Unusual Site of Abscess Development

1,2,6Reader, 3Assistant Professor, 4Senior Lecturer 5Senior Research Fellow 1,2Department of Prosthodontics, Narsinhbhai Patel Dental College & Hospital, Sankalchand Patel University, Visnagar Gujarat, India 3Department of Neurosurgery, Dr. Susheela Tiwari Government Hospital, Haldwani, Uttarakhand, India 4Department of Oral Pathology, Surendera Dental College and Research Institute, Sri Ganganagar, Rajasthan, India 5Department of Pathology, All India Institute of Medical Sciences New Delhi, India 6Department of Public Health Dentistry, Sarjug Dental College and Hospital, Darbhanga, Bihar, India Corresponding Author: A Chaudhary, Reader, Department of Prosthodontics, Narsinhbhai Patel Dental College & Hospital Sankalchand Patel University, Visnagar, Gujarat, India, Phone: +91-9694959495, e-mail: akashat.chaudhary@gmail.com ABSTRACT

PODIA: Power Optimization through Differential Imbalanced Amplifier

Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic added for short path constraint, metastability, etc., desired accuracy level and a wider voltage scaling range is not achievable through conventional DVFS method, resulting in reduced power savings. This paper demonstrates a power optimization technique using an accurate differential sensing latch called PODIA. A typical safety margin of 200ps is achieved between the main flip-flop and shadow latch without any short path constraint. Metastability resilience is achieved while clocking is also simplified. A gain of 90ps to 30 ps with respect to the conventional RAZOR architecture [3] is achieved across the operating voltage range of 0.6 to 1V respectively. Self timed differential amplifier based latching is used to reduce power consumption by using early detection of data transition. It is shown through spice simulations that power saving of up to 50% (across Process, Voltage and Temperature corners) can be achieved in a 16 × 16 multiplier made using the proposed flip-flop.

Design and development of micro pulse lidar for cloud and aerosol studies

A micro pulse lidar (MPL) has been indigenously designed and developed at the National Physical Laboratory, New Delhi using a 532 nm, 500 pico second pulsed laser having average power of 50mW (at 7.5 KHz PRR). Photon counting technique has been incorporated using the conventional optics, multichannel scaler (Stanford Research Systems SR430) and high sensitive photomultiplier tube. The sensitivity, range and bin etc are computer controlled in the present system. The interfacing between MPL and computer has been achieved by serial (RS232) and parallel printer port. The necessary software and graphical user interface has been developed using visual basic. In addition to this the telescope cover status sensing circuit has been incorporated to avoid conflict between dark count and background acquisition. The micro pulse lidar will be used for the aerosol, boundary layer and the cloud studies at a bin resolution of 6 meters. In the present communication the details of the system and preliminary results will be presented.

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis

With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing Bitmap Diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete Bitmap to the tester. The proposed methodology supports testing through a very low cost ATE. This architecture is partitioned to achieve sharing among various memories and at-speed testing.