Navneet Gupta

Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications

In this paper, an ultra-low-leakage TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad memory is proposed. DPSRAM cells are designed using TFETs to reduce the leakage power in the memory array as compared to CMOS. Peripheral circuits are designed using 28nm FDSOI technology to increase speed and to reduce area as compared to full TFET based memories. Performance and stability of the memory is analyzed for different supply voltages to support dynamic voltage frequency scaling (DVFS). Imbalanced single-ended sensing is proposed in the paper and different write-assist techniques are analyzed for the proposed TFET memory cell. In the analysis of TFET DPSRAM bitcell at 1V supply voltage the evaluated noise margins are 114mV and 185 mV for read and write, respectively, with a 5 orders of magnitude reduction in leakage as compared to a similar CMOS bitcell. Results of performance evaluation of the designed 32Kb TFET/CMOS DPSRAM show a gain of up to 79.2% in write speed using write assist at sub-1V supply voltages and less than 1 ns read/write cycle time for more than 1V supply voltages.

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications

This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance from 4Kb SRAM designed in 28nm FDSOI CMOS process using MOSFETs & Tunnel FETs (TFETs). The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. A 0.35 fA/bit memory array leakage current was achieved showing a 14x to 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells. Minimum read and write access pulse is evaluated at 1.27ns at sub-1V supply voltage.

Ultra-compact SRAM design using TFETs for low power low voltage applications

This paper presents a hybrid TFET/CMOS SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like the IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while periphery is maintained in standard CMOS. The simulation extractions for power and speed are done including wiring and device parasitics extracted from 4Kb SRAM designed in 28nm FDSOI CMOS process. The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. The memory array leakage current is less than 1 fA/bit at sub-0.5V supply voltages, showing up-to 50x and 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells, respectively. Bitcell area is reduced by 3x in comparison to existing TFET designs. Evaluated static noise margin (SNM) is 100mV for supply voltages range from 0.2V to 0.6V. Minimum read and write access pulse is evaluated at 15ns at 0.45V supply voltage.

Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications

In this paper, we propose a novel TFET Flip-Flop (TFET-FF) designed to address the requirements of ULP (Ultra-Low-Power) applications, like IoT (Internet of Things), while maintaining high performance. The performance of the proposed design in terms of power, area and speed is compared with different flip-flop designs present in literature for MOSFETs, TFETs and FinFETs. The proposed flip-flop supports voltage scaling and works for supply voltages from 0.3V to 0.6V. Leakage is improved by 4 to 7 decades in comparison to state-of-the-art TFET, FinFET and MOSFET designs. With neither feedback for latch implementation nor device stacking, the TFET-FF speed is comparable or exceeds the speed of High-Performance FinFET implementation for VDD = 0.3V/0.5V. The number of transistors used for the proposed TFET-FF is reduced by 50% in comparison to CMOS and FinFET implementations.

TFET NDR skewed inverter based sensing method

Many of CMOS SRAMs (like 8T-SRAMs), DRAMs, non-volatile memories and TFET SRAMs use single ended read. Optimization of such sensing schemes is critical. Conventional single ended sensing requires either full discharge of bitline (BL) or voltage/current reference in order to use differential sense amplifier. There is speed and/or power penalty because of either full discharge of BL or complex sense amplifier using references. In this paper, a TFET negative differential resistance property based skewed inverter single-ended read scheme has been proposed. This sensing scheme detects read with less than 200mV BL discharge with inverter based sensing. This results in simplified single ended scheme with speed and BL discharge similar to differential sensing schemes. Less than 400ps read delay is achieved for 200mV BL discharge at 1V supply.

CMOS Sensor Nodes With Sub-Picowatt TFET Memory

This paper describes the applicability of tunnel FETs (TFET) to ultra-low-power sensor-node embedded static random-access memories (SRAMs). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a five orders of magnitude reduction in standby current. A lookup table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at VDD = 1 V or lower. The read and write static noise margins are evaluated at 120 and 200 mV, with the operation speeds of 3.8 GHz and 800 MHz at VDD = 1 V in read and write, respectively. The cell leakage is less than 5 fA at VDD = 1 V. A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 4 fW/cell or 4.1 pW for a 1-kb array at 1 V supply voltage.

Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes

This paper describes the applicability of Tunnel FETs (TFET) to ultra-low-power sensor-node embedded Static Random-Access Memories (SRAM). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at Vdd=1V or lower. The Read and Write Static Noise Margins (SNM) are evaluated at 120mV and 200mV, with the operation speed of 3.8GHz and 800MHz Vdd=1V in read and write, respectively. The cell leakage is less than 5fA at Vdd=1V. A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 2 fW/cell or 48 pW for a 4 kB array.

Tunnel FET based ultra-low-leakage compact 2T1C SRAM

In this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low leakage below 1fA/bit is achieved in the proposed design. Read and write cycle times of sub-2ns and sub-4ns are designed.

1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell

Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption per search, giving an improvement of 4.6× [2], 8.3× [3], 5.9× [4] and 14.3× [5] with respect to Ref. [2]-[5]. Similarly, the search speed is improved by 4.2× [2], 3.12× [4], and 6.24× [5].

Tunnel FET based refresh-free-DRAM

A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275μm2 is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal.