Prashant Saxena

Repeater scaling and its impact on CAD

We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing that mere capacity scaling of current algorithms and methodologies is insufficient to handle the new challenges. Finally, we suggest a few approaches to tackle these challenges by constructing a case for abstract fabrics.

The scaling challenge: can correct-by-construction design help?

We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correct-by-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

A postprocessing algorithm for crosstalk-driven wire perturbation

Much of the previous work on crosstalk minimization attempted to handle crosstalk during the process of routing the nets. However, this necessitates the estimation of the expected crosstalk due to nets that are yet to be routed. In contrast, post-processing algorithms can use accurate crosstalk measurements to respace the wires, thus improving the crosstalk even in routings produced by crosstalk-aware routers. However, the postprocessing algorithms presented so far have been restricted either by the use of a gridded model or by the difficulty of optimizing the highly nonlinear crosstalk-based objective functions. We address the problem of minimizing the peak crosstalk in a routed region by respacing its critical nets and their neighbors. We study the variation of the crosstalk in a net and its neighbors when one of its trunks is perturbed, showing that the trunks perturbation range can be efficiently divided into subintervals having monotonic or unimodal crosstalk variation. This result enables us to determine the optimum location for the trunk without needing to solve any nonlinear equations. Using this, we construct an algorithm to minimize the peak crosstalk in the nets of a gridless channel. Although we present our results in terms of channel routing, our theory is also applicable to more general routing models. Furthermore, our crosstalk model subsumes the models used in most prior works on noise-aware routing. Our experiments verify the effectiveness of our approach.

Crosstalk minimization using wire perturbations

We study the variation of the crosstalk in a net and its neighbors when one of its trunks is perturbed, showing that the trunks perturbation range can be efficiently divided into subintervals having monotonic or unimodal crosstalk variation. We can therefore determine the optimum trunk location without solving any non-linear equations. Using this, we construct and experimentally verify an algorithm to minimize the peak net crosstalk in a gridless channel.

On integrating power and signal routing for shield count minimization in congested regions

With worsening crosstalk in nanometer designs, it is increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by inserting shields adjacent to these wires. However, the number of shielded wires can become extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We propose a new abstraction for the block-level global and detailed routing hierarchy that allows accurate early estimation of crosstalk. Furthermore, we postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer while guaranteeing adequate power delivery. Our approach has proven effective while designing some high-frequency blocks of a commercial gigahertz range microprocessor using a 0.18-/spl mu/m process technology.

Modeling repeaters explicitly within analytical placement

Recent works have shown that scaling causes the number of repeaters to grow rapidly. We demonstrate that this growth leads to massive placement perturbations that break the convergence of todays interleaved placement and repeater insertion flows. We then present two new force models for repeaters targeted towards analytical placement algorithms. Our experiments demonstrate the effectiveness of our repeater modeling technique in preserving placement convergence (often also accompanied by wirelength improvement) at the 45 and 32 nm technology nodes.

An efficient technology mapping algorithm targeting routing congestion under delay constraints

Routing congestion has become a serious concern in todays very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic-programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100-nm technology show that the algorithm can improve track overflows significantly as compared to conventional technology mapping while satisfying delay constraints.

A predictive distributed congestion metric with application to technology mapping

Due to increasing design complexities, routing congestion has become a critical problem in very large scale integration designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization. Our technology mapping algorithms are guided by a probabilistic congestion map for the subject graph to identify the congested regions, where congestion-optimal matches are favored. Experimental results on a set of benchmark circuits in a 90-nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows with marginal gate-area penalty as compared to conventional area-oriented technology mapping. For delay-oriented mapping, our algorithm improves track overflows by 20%, on an average, in addition to preserving or improving the delay, as compared to the conventional method.

A system-level solution to domino synthesis with 2 GHz application

System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.