Prashant Upadhyay

A novel design method for optimal IIR system identification using opposition based harmony search algorithm

Abstract In this paper a population based evolutionary optimization methodology called Opposition based Harmony Search Algorithm (OHS) is applied for the optimization of system coefficients of adaptive infinite impulse response (IIR) system identification problem. The original Harmony Search (HS) algorithm is chosen as the parent one and opposition based approach is applied to it with an intention to exhibit accelerated near global convergence profile. During the initialization, for choosing the randomly generated population/solution opposite solutions are also considered and the fitter one is selected as apriori guess for having faster convergence profile. Each solution in Harmony Memory (HM) is generated on the basis of memory consideration rule, a pitch adjustment rule and a re-initialization process which gives the optimum result corresponding to the least error fitness in multidimensional search space. Incorporation of different control parameters in basic HS algorithm results in balancing of exploration and exploitation of search space. The proposed OHS based system identification approach has alleviated from inherent drawbacks of premature convergence and stagnation, unlike Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Differential Evolution (DE). The simulation results obtained for some well known benchmark examples justify the efficacy of the proposed OHS based system identification approach over GA, PSO and DE in terms of convergence speed, identifying the system plant coefficients and mean square error (MSE) fitness values produced for both same order and reduced order models of adaptive IIR filters.

A design of low swing and multi threshold voltage based low power 12T SRAM cell

Proposed low power 12T MTCMOS based SRAM cell.Display Omitted A novel low power 12T MTCMOS based SRAM cell is proposed.Charge recycling technique used for reducing the current leakage during transition mode.Use voltage sources to reduce the dynamic power dissipation.Improving the stability of SRAM cell. This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

An efficient differential evolution with wavelet mutation algorithm for optimal IIR filter design

In this paper, an improved version of differential evolution (DE) algorithm which incorporates wavelet-based mutation strategy called differential evolution with wavelet mutation (DEWM) is proposed for the design of digital infinite impulse response (IIR) filters. Unlike fixed value of scaling factor in standard DE, the proposed optimisation technique DEWM adopts iteration dependent scaling factor governed by the wavelet function during the mutation process. This modification in the mutation process not only ensures the faster searching in the multidimensional search space but also the solution produced is very close to the global optimal solution. The effectiveness of this algorithm is justified with a comparative study of some well established algorithms, namely, real coded genetic algorithm (RGA), conventional particle swarm optimisation (PSO) and standard DE with a superior DEWM-based outcome for the designed 8th order IIR low pass (LP), high pass (HP), band pass (BP) and band stop (BS) filters. Simulation results affirm that the proposed DEWM algorithm outperforms its counterparts not only in terms of quality output, i.e., sharpness at cut-off, pass band ripple and stop band attenuation but also in convergence speed with assured stability.

Power and Stability Analysis of a Proposed 12T MTCMOS SRAM Cell for Low Power Devices

This paper focuses on the power dissipations at different temperatures and stability analysis at different pull-up ratios of a novel low power 12T MTCMOS SRAM cell. Because of MTCMOS technology, the SRAM cell is having low VT (LVT) transistors and there are two high VT (HVT) Sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static energy dissipation of the cell. In the proposed structure two additional voltage sources are also used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. The reduction in swing causes the reduction in dynamic power dissipation. Because of very low leakage currents in MTCMOS technology, the stability of data retention is also enhanced. Simulation results of power dissipation and stability of the proposed SRAM cell have been determined and compared to those of some other exiting models of SRAM cell. The proposed cell dissipates less power at different temperatures and better stability at different pull-up ratios than the other SRAM models. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

A novel social emotional optimisation algorithm for IIR system identification problem

In this paper an evolutionary optimisation methodology based on social emotional optimisation algorithm (SEOA) is applied to the infinite impulse response (IIR) system identification problem. In SEOA methodology, behaviour of human beings for achieving higher social status in society is structured. In this virtual world, the individual with the highest rank in society gives the optimal solution in multidimensional search space. Earning the highest social status by means of cooperation and competition with others not only results in better exploration and exploitation of problem space but also ensures faster convergence to optimal solution. The proposed SEOA based system identification approach has resolved the inherent drawbacks of premature convergence and stagnation, unlike genetic algorithm (GA), particle swarm optimisation (PSO) and differential evolution (DE). The simulation results obtained for some well known benchmark examples justify the efficacy of the proposed system identification approach using SEOA over GA, PSO and DE in terms of convergence speed, unknown plant coefficients and mean square error (MSE) values produced for both the same order and reduced order models of adaptive IIR filters.

Low power with high stability 12T MTCMOS based SRAM cell for write operation

This paper focuses on the power dissipations at different supply voltages, bit line capacitances and stability analysis at different pull-down ratios of a novel low power 12T MTCMOS SRAM cell. Because of MTCMOS technology, the SRAM cell is having low VT (LVT) transistors and there are two high VT (HVT) Sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static energy dissipation of the cell. In the proposed structure two additional voltage sources are also used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. The reduction in swing causes the reduction in dynamic power dissipation. Because of very low leakage currents in MTCMOS technology, the stability of data retention is also enhanced. Simulation results of power dissipation and stability of the proposed SRAM cell have been determined and compared with those of some other exiting models of SRAM cell. The proposed cell dissipates less power at different supply voltages, bit line capacitance and better stability at different pull-down ratios than the other SRAM models. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

Stability Analysis of a Novel Proposed Low Power 10T SRAM Cell for Write Operation

This paper focuses on the analysis of stability of a proposed low power 10T SRAM cell during write operation. In the proposed structure there are two voltage sources, one connected with the bit line and the other connected with the bitbar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which increase the threshold voltages of the pull down transistors and cause the reduction in sub-threshold leakage current and static power dissipation. In this paper we use the approach of write static noise margin, bit line voltage write margin and word line voltage write margin for analyzing the stability of the proposed SRAM cell. These two extra voltage sources control the voltage swing on the output node and improve the noise margin during the write operation. Simulation has been done in 45nm CMOS technology with 1.0 volt power supply in Microwind 3.1 software. Simulation results have been compared to those of other existing SRAM cells.

A 12T MT-CMOS low power and low leakage SRAM cell

This paper focuses on the design of low power and stable, novel 12T multi-threshold CMOS (MTCMOS)-based static random access memory (SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. Reduction in swing voltage reduces the dynamic power dissipation. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep-to-active (OFF-to-ON condition) and active-to-sleep (ON-to-OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. So in the proposed SRAM cell both dynamic and static powers have been reduced. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. The circuit simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for the purpose of schematic and layout designs.

A novel low power 8T SRAM cell design using lower and upper self controllable voltage level techniques in 45 nm technology

This paper proposes a novel low power 8T SRAM cell for write operation. In the proposed structure, two voltage sources VS1 and VS2 are connected with the bit line and the bit bar line, respectively. These voltage sources reduce the swing voltage and reduction in swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell. Also, two different leakage power reduction techniques called upper self controllable voltage level (USVL) and lower self controllable voltage level (LSVL) have been proposed and applied individually and in combination with the proposed 8T SRAM for the reduction of leakage current. Both the leakage current and power dissipation results are compared with those of conventional 6T and 7T SRAM cells reported in different literatures. Static noise margin is also analysed during write operation for stability purpose. The proposed SRAM cell has lesser leakage current in comparison to conventional 6T SRAM cell and also dissipates the least amount of power and yields better stability in comparison to both 6T and 7T SRAM cells. The authors use 45 nm CMOS technology with 0.5 volt power supply for simulation purpose. Microwind 3.1 software is used for schematic design and simulation.

A novel 10T SRAM cell for low power circuits

This paper presents on the analysis of static and dynamic power dissipations in the proposed 10T SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which result in increase in the threshold voltage of the transistors and thus cause the reduction in static power dissipation. Simulation has been done in 90nm CMOS technology with 1 volt power supply in Microwind 3.1 software. Simulation results have been compared with those of other existing SRAM cells.