Pratheep Balasingam

Investigation of Proximity Effects in a 6T SRAM Cell Using Three-Dimensional TCAD Simulations

In this paper, we study the impacts of proximity effects on the electrical characteristics Id-Vg and the static noise margin of a six-transistor (6T) bulk complementary metal-oxide-semiconductor (MOS) static random access memory (SRAM) cell using 3-D process and device technology computer-aided design (TCAD) simulations. We show that when a 6T SRAM cell is simulated as a single continuous 3-D structure, effective stresses in channels are reduced due to close proximity of n-channel and p-channel MOS transistors in the cell with respect to simulations of transistors as discrete 3-D structures. Furthermore, we find that doping in channels of SRAM transistors is reduced by well proximity and implant shadowing. Stress and doping proximity effects have opposite contributions to device performance. We estimate the influence of proximity effects for typical 32-nm technology to be more than 10% for certain electrical cell characteristics. We thus conclude that, to accurately predict electrical cell behavior via TCAD simulations, the 6T SRAM cell should be a single continuous 3-D structure, instead of a set of six discrete transistors, which are simulated as individual 3-D devices and connected via a netlist.

Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent

IC layouts are typically defined with simple shapes such as rectangles and 45° triangles. Fundamental limitations in the imaging process unavoidably prevent the exact rendering of these shapes on the wafer, and this necessitates an interpretation of what should appear on silicon. For example, an OPC tool must interpret a square corner as something more rounded, otherwise the pursuit of the ideal shape may lead to bridging and/or Mask Rule Check (MRC) violations. A solution to this is to move the target points for Optical Proximity Correction (OPC) off from the GDS edges and onto mathematically described curves inscribed within the corners of the design polygon and use these as the target for OPC correction. Suitable values for the radius of these curves depend on the model used, the geometry they are applied to, and the requirements of the device the shape builds. An uncorrected square corner gives a printed contour whose radius of curvature, nearest the design corner, provides a target radius for a low impact OPC correction. Line ends, right angled bends in tracks and end caps all need separate optimization in terms of the best radius of target curve to use. By understanding whether the design priority is for CD control (such as poly gate) or for positional accuracy (such as contact enclosure) the OPC correction parameters and final target shape can be modified in such a way to best realize these interpreted goals.

Reliability analysis of bumping schemes under chip package interaction

Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties.

Determination of Cu-line EM Lifetime Criteria Using Physically Based TCAD simulations

A physically based simulation methodology provides fast and practical EM lifetime prediction. We identified an “EM-aware” region to define the length dependence of Cu-lines under high current stress. For eventual calibration of 2× nm node Cu-lines, we analyzed the sensitivity trends of vacancy and void profiles as well as the mass transport mechanisms using a 3D TCAD tool. This includes electron flow dependency to explain line and via depletion effects for void formations under various EM stress conditions. We report a non-linearity in the length dependence on the EM failure jL product at ~9000 A/cm and a slight temperature dependence on the Blech Threshold (jL)c at ~2000 A/cm extracted at 300°C in the EM aware region.

Computational analysis of mechanical and electromigration reliability problems

The reliability of complex interconnect structures at all levels of the chip integration hierarchy has become a major concern due to the use of fine feature sizes, diverse materials, and complex 3D architectures. Reliability issues range from stress related failures such as dielectric cracking and interface debonding during manufacturing to electrical and mechanical failures such as electromigration and void formation during operation. This paper summarizes computational results obtained using a unified physics-based 3D simulation framework.

Three-dimensional TCAD Process and Device Simulations

Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.