Praveen Bhojwani

Interfacing cores with on-chip packet-switched networks

With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key contributors to latency. With the goal of reducing this latency we examine the packetization strategies in the NoC communication. In this paper, three schemes of implementations are analyzed, and the costs in terms of latency, and area are projected through actual synthesis.

IntellBatt: towards smarter battery design

Battery lifetime and safety are primary concerns in the design of battery operated systems. Lifetime management is typically supervised by the system via battery-aware task scheduling, while safety is managed on the battery side via features deployed into smart batteries. This research proposes IntellBatt; an intelligent battery cell array based novel design of a multi-cell battery that offloads battery lifetime management onto the battery. By deploying a battery cell array management unit, IntellBatt exploits various battery related characteristics such as charge recovery effect, to enhance battery lifetime and ensure safe operation. This is achieved by using real-time cell status information to selects cells to deliver the required load current, without the involvement of a complex task scheduler on the host system. The proposed design was evaluated via simulation using accurate cell models and real experimental traces from a portable DVD player. The use of a multi-cell design enhanced battery lifetime by 22% in terms of battery discharge time. Besides a standalone deployment, IntellBatt can also be combined with existing battery-aware task scheduling approaches to further enhance battery lifetime.

A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems

Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system components and routing of system communication affect system performance and power consumption. This research provides a heuristic to determine the neighborhood configuration for each component. By controlling the communication bandwidth allocation, simulation results with synthetic and real workloads indicate that our heuristic is able to control the peak power consumption, but at cost of throughput degradation.

Core Network Interface Architecture and Latency Constrained On-Chip Communication

This paper proposes a core network interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds

A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip

Concurrent on-line testing (COLT) of complex systems-on-a-chip (SoC) designs under lowering noise margins and degrading lifetimes of on-chip components, provides the ideal solution for the monitoring of system health while managing intrusion into executing applications. Deploying test infrastructure-IPs (TI-IPs) into designs has demonstrated the feasibility of using COLT in SoCs. Identifying potential hazards and ensuring correct operation of COLT is critical to providing reliable health monitoring. With the emergence of networks-on-a-chip (NoC) as communication infrastructures not only suitable for application related on-chip communication, but also test access mechanisms to on-chip cores, the experimental setup in this research, deploys TI-IP in a NoC environment and demonstrates TI-IP operation, its communication protocol specification and other related costs.

IntellBatt: Toward a Smarter Battery

IntellBatt, a novel multicell battery design, exploits cell characteristics to increase battery lifetime, ensure safe operation, and improve performance. Simulations using Li-ion cells in a portable DVD player show a 22 percent battery lifetime enhancement.

Robust Concurrent Online Testing of Network-on-Chip-Based SoCs

Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in reliability motivate the development of solutions to ensure reliable operation. A precursor to any proposed recovery scheme would require the identification of failures in the system. Non-concurrent in-field testing is an impractical solution due to prohibitive costs in terms of test power and test time. This novel research proposes the use of concurrent online testing (COLT) to circumvent these issues. A test infrastructure-intellectual property (TI-IP) is deployed within network-on-chip (NoC)-based SoC designs to provide online test support while managing intrusion of test into executing applications within the system. This research describes the architecture and operation of a TI-IP capable of COLT. To address scalability of this solution, we show how these would operate when more than one is deployed in an SoC. In the absence of benchmarks for the analysis of COLT, two baseline and eight TI-IP configuration variations within SoC test configurations were developed using application and test benchmarks from the research domain. The power profiles from the NoCSim simulation environment are reported here demonstrating how different configurations of TI-IPs would operate. A robust TI-IP protocol is also specified and possible hazards and their mitigations are identified.

SAPP: scalable and adaptable peak power management in nocs

To address peak power concerns in networks-on-chip (NoCs), dynamic peak power management schemes that handle varying power requirements are essential. Previous schemes use deterministic peak power budget management techniques that do not scale or adapt efficiently to changing power budget requirements. Using a non-deterministic and independent approach, this research proposes SAPP, a Scalable and Adaptable Peak Power management technique for NoCs. Evaluation of SAPP on uniform and non-uniform varying injection loads demonstrates flit latency and effective throughput improvements averaging 47% and 36%, respectively. Efficient power budget utilization makes SAPP an ideal technique for peak power management in NoCs under varying traffic patterns.

An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs

To address the reliability concerns that affect the lifetime of complex systems-on-a-chip (SoC) designs, a concurrent on-line SoC test scheme is essential to circumvent the prohibitive costs - test time and test power

A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications

associated with off-line SoC test. A test infrastructure IP (TI-IP) is deployed within the network-on-chip (NoC) based SoC design to provide on-line test support while managing the intrusion of test into the executing applications within the system. This research describes the architecture and operation of a TI-IP capable of testing SoCs and demonstrates its operation in two SoC test configurations developed using research domain application and test benchmarks