Saraju P. Mohanty

A DCT domain visible watermarking technique for images

The growth of computer networks has boosted the growth of the information technology sector to a greater extent. There is a trend to move from conventional libraries to digital libraries. In digital libraries images and text are made available through the Internet for scholarly research. At the same time care is taken to prevent the unauthorized use of the images commercially. In some cases the observer is encouraged to patronize the institution that owns the material. To satisfy both these needs simultaneously the owner needs to use visible watermarking. Visible watermarking is a type of digital watermarking used for protection of publicly available images. We describe a visible watermarking scheme that is applied into the host image in the DCT domain. A mathematical model has been developed for this purpose. We also propose a modification of the algorithm to make the watermark more robust.

Biosensors: a tutorial review

This paper discusses various biosensors in detail, where the biosensor consists of bioelement and a sensor element. The bioelement may be an enzyme, antibody, living cells etc., and the sensing element may be electric current, electric potential, and so on. This survey initially introduces the basic concept of the biosensors. High-level overviews of different types of biosensors are given and the working principles, constructions, advantages and applications of many biosensors are also presented. In addition to these MEMS have given rise to a whole new class of biosensors which involve the transduction of mechanical energy and are based on mechanical phenomena.

A dual watermarking technique for images

Digital watermarking is the technique in which a visible/invisible signal (watermark) is embedded in a multimedia document for copyright protection. In this paper, we propose a watermarking scheme called “dual watermarking”. Dual watermark is a combination of a visible watermark and an invisible watermark,

Hardware assisted watermarking for multimedia

Digital media offer several distinct advantages over analog media, such as high quality, ease of editing, and ease of processing operations such as compression and high fidelity copying. Digital data is commonly available through digital TV broadcast, CD, DVD, and computing devices such as personal computers. The ease by which a digital media object can be duplicated and distributed has led to the need for effective digital rights management tools. Digital watermarking is one such tool. Watermarking is the process of embedding extra data called a watermark into a multimedia object, like image, audio, or video, such that the watermark can later be detected or extracted in order to make an assertion regarding the object. During the last decade, numerous software based watermarking schemes have appeared in the literature and watermarking research has attained a certain degree of maturity. But hardware based watermarking systems have evolved more recently only and they are still at their infancy. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. In this paper, we survey the hardware assisted solutions proposed in the literature for watermarking of multimedia objects. The survey is preceded by an introduction to the background issues involved in digital watermarking.

VLSI architecture and chip for combined invisible robust and fragile watermarking

Research in digital watermarking is mature. Several software implementations of watermarking algorithms are described in the literature, but few attempts have been made to describe hardware implementations. The ultimate objective of the research is to develop low-power, high- performance, real-time, reliable and secure watermarking systems, which can be achieved through hardware implementations. The development of a very-large-scale integration architecture for a high-performance watermarking chip is presented which can perform both invisible robust and invisible fragile image watermarking in the spatial domain. The watermarking architecture is prototyped in two ways: (i) by using a Xilinx field-programmable gate array and (ii) by building a custom integrated circuit. This prototype is the first watermarking chip with both invisible robust and invisible fragile watermarking capabilities.

VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder

The research in digital watermarking is well matured. Several watermarking algorithms have been proposed for image, video, audio and text in the current literature. Digital watermarking is the process that embeds data, called a watermark, into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. The number of software implementations of the proposed algorithms is significantly large, whereas a hardware implementations is lacking. Hardware implementation has advantages over software implementation in terms of low power, high performance, and reliability. We have developed a hardware system that can insert both robust and fragile invisible watermarks in the image. The hardware module can be easily incorporated in a JPEG encoder to develop a secure JPEG encoder. The watermark module is implemented using 0.35 /spl mu/m CMOS technology. To our knowledge, this is the first watermarking chip implementing both invisible-robust and invisible-fragile watermarks.

Invisible watermarking based on creation and robust insertion-extraction of image adaptive watermarks

This article presents a novel invisible robust watermarking scheme for embedding and extracting a digital watermark in an image. The novelty lies in determining a perceptually important subimage in the host image. Invisible insertion of the watermark is performed in the most significant region of the host image such that tampering of that portion with an intention to remove or destroy will degrade the esthetic quality and value of the image. One feature of the algorithm is that this subimage is used as a region of interest for the watermarking process and eliminates the chance of watermark removal. Another feature of the algorithm is the creation of a compound watermark using the input user watermark (logo) and attributes of the host image. This facilitates the homogeneous fusion of a watermark with the cover image, preserves the quality of the host image, and allows robust insertion-extraction. Watermark creation consists of two distinct phases. During the first phase, a statistical image is synthesized from a perceptually important subimage of the image. A compound watermark is created by embedding a watermark (logo) into the statistical synthetic image by using a visible watermarking technique. This compound watermark is invisibly embedded into the important block of the host image. The authentication process involves extraction of the perceptive logo as well statistical testing for two-layer evidence. Results of the experimentation using standard benchmarks demonstrates the robustness and efficacy of the proposed watermarking approach. Ownership proof could be established under various hostile attacks.

A secure digital camera architecture for integrated real-time digital rights management

This paper presents a novel concept of a secure digital camera (SDC) with a built-in watermarking and encryption facility. The motivation is to facilitate real-time digital rights management (DRM) by using the SDC right at the source end of multimedia content. The emerging field of DRM systems addresses the issues related to the intellectual-property rights of digital content. The use of digital watermarking along with encryption for effective DRM is proposed. In this context, a novel discrete cosine transform domain invisible-robust watermarking method that uses cryptography and watermarking methods simultaneously to provide a double-layer of protection to digital media is presented. The proposed method securely hides binary images in color image media and securely extracts and authenticates it by using a secret key. Experimental results prove that the proposed technique is resilient to stringent watermarking attacks. Hence, it is an effective method for providing protection of ownership rights. The corresponding application-specific architectures for invisible-robust watermarking and Rijndael advanced encryption standard (AES) towards the prototyping of the SDC are presented. The proposed architectures are modeled and synthesized for field programmable gate array (FPGA). The soft cores in the form of hardware description language resulting from this research can serve as intellectual-property core and can be integrated with any multimedia-producing electronic appliances which are built as embedded systems using system-on-a-chip (SoC) technology.

A dual voltage-frequency VLSI chip for image watermarking in DCT domain

In this brief, we present a new VLSI architecture that can insert invisible or visible watermarks in images in the discrete cosine transform domain. The proposed architecture incorporates low-power techniques such as dual voltage, dual frequency, and clock gating to reduce the power consumption and exploits pipelining and parallelism extensively in order to achieve high performance. The supply voltage level and the operating frequency are chosen for each module so as to maintain the required bandwidth and throughput match among the different modules. A prototype VLSI chip was designed and verified using various Cadence and Synopsys tools based on TSMC 0.25-/spl mu/m technology with 1.4 M transistors and 0.3 mW of estimated dynamic power.

A single ended 6T SRAM cell design for ultra-low-voltage applications

In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one’ is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.