Praveen Elakkumanan

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address single even upsets (SEUs). Robust combinational logic designs capable of tolerating single event transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due to the radiation hardening is minimized by reusing existing components (uses existing scan portion for SET tolerance). As shown by the simulation results, the proposed SET tolerant flip-flop has no performance overheads and simulation results that show the area overheads in ISCAS benchmark circuits are also presented

High speed robust current sense amplifier for nanoscale memories: a winner take all approach

The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bit line capacitance and process variations. Current sensing in SRAMs is promising to achieve high-speed operation in low-voltage application. In this paper, we propose a process variation tolerant, high performance and scalable current sense amplifier that uses a winner take all (WTA) approach for nanoscale SRAMs. Simulation of worst-case threshold voltage mismatch on our WTA sense amplifier shows that it could tolerate up to 10% variation in the threshold voltage, which is expected within die in a 70nm process. Detailed analysis of variation in the effective channel length (L/sub eff/) and supply voltage variation are also presented. A comparison of the sensing delay and energy consumption in 70nm technology shows that our WTA sense amplifier provides around 70-80% improvement in the sensing speed and consumes 28-70% less energy than the traditional voltage mode and current sense amplifiers.

NC-SRAM - a low-leakage memory circuit for ultra deep submicron designs

In this paper, we present a novel N-controlled SRAM (NC-SRAM) design for reducing the subthreshold leakage in cache and embedded memories using a dual-V/sub t/ process. We combine the use of high V/sub t/ transistors in the leakage path and gating the supply voltage to reduce leakage in unused SRAM cells. This circuit-level technique overcomes the potential limitations in the existing techniques for reducing leakage in memory circuits. In this design, the data stored in the cell is retained even when the memory is put in the stand-by mode, with no additional complexity or circuit overhead. Simulation results indicate that NC-SRAM has better leakage savings as compared to other techniques. In addition, our results on 100 nm and 70 nm processes show 21% and 18% reduction in total power and 77% and55 % reduction in leakage power, respectively, with very minimal impact on performance and area, as compared to a conventional 6T-SRAM.

Leakage Reduction for Domino Circuits in Sub-65nm Technologies

With aggressive technology scaling, leakage power is fast becoming a significant component of the total power consumption of high-performance circuits. In this paper, we analyse the gate leakage and subthreshold leakage current characteristics of domino circuits and propose a circuit which reduces both gate and subthreshold leakage, and thus the overall leakage of sub-65 nm domino circuits. Simulation results based on 45 nm BSIM4 models show that the gate leakage, subthreshold leakage and overall leakage are reduced by up to 94%, 64% and 89% respectively, as compared to the conventional dual-Vt designs. The proposed circuit maintains the inputs, the dynamic node and the output node at logic high, to reduce the gate leakage. It reduces subthreshold leakage by enhancing the stack effect and source biasing effect.

A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

Performance of system-on-chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasisynchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18//spl mu/m technology.

RG-SRAM: a low gate leakage memory design

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep sub-micron (VDSM) cache and embedded memories.

CHIDDAM: a data mining based technique for cache hierarchy determination in commercial applications

In this paper, we present a cache hierarchy design using data mining (CHIDDAM) methodology to improve the memory efficiency for a given type of commercial application and its data set characteristics. Performance analysis, workload characterization, decision tree induction (a classification data mining method), and a greedy search algorithm are used in determining the optimal number of levels and sizes of the cache in the hierarchy. SimICS, a full system simulator, is used to simulate an /spl times/86 machine loaded with Enterprise Linux operating system. Popular representative applications in data mining, such as, C4.5 and Apriori are used as benchmark applications for our simulation analysis. However, the proposed methodology is generic and can be applied to other applications for determine the design details of memory subsystems.

SRAM Local Bit Line Access Failure Analyses

Due to the increasing process parameter variations and bitline capacitance, design of fast, reliable and robust read/write circuits for nanoscale SRAMs is a challenge. In this paper, we have investigated the effect of threshold voltage variations on the stability of read and write access schemes in SRAM designs. We considered three small signals read out and two write schemes to establish the SRAM local bitline failure trends and behavior under aggressive timing constraints and in the presence of process variations. The critical transistors in both the memory cell and the sense circuits are determined using corner analyses. Detailed simulation analyses are then performed by randomly varying the threshold voltages of these critical transistors, and the failing probabilities and points are then determined. Observations and conclusions on the failure trends of both the read and write operations are presented

DG-SRAM: a low leakage memory circuit

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. This gate leakage current coupled with the subthreshold leakage, results in a dramatic increase in total leakage power. Hence, efficient power reduction strategies that directly address the gate leakage component are necessary. In this paper, we present a diode-gated SRAM (DG-SRAM) that uses two additional NMOS (or PMOS) transistors to decrease the gate leakage in very deep sub-micron (VDSM) cache and embedded memories. Our simulation results on 65nm process (Berkeley Predictive Technology Model) for an oxide thickness of 1.5nm indicate a reduction of about 69% of the gate leakage and 65% of total leakage for NMOS-connected DG-SRAM as compared to the conventional SRAM, with minimal area overhead and no significant loss in performance or stability.

Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)

Summary form only given. This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent design for manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their impact on layout quality, and present currently practiced DFM techniques to mitigate the effect of these variations. We also discuss various manufacturing-aware physical and circuit design methodologies and techniques for parametric yield improvement. This includes correct-by-construction methodologies such as Restricted Design Rules (RDRs) as well as manufacturing aware design approaches. In addition, we will briefly mention some of the many accepted and possible mitigation techniques in design post processing (after tape-out) and will introduce the concept of manufacturing for design (MFD) through design-intent processing.