Predrag Radosavljevic

Performance of IEEE 802.11b wireless LAN in an emulated mobile channel

The performance of 802.11b wireless LANs is well understood for indoor environments. However, their behavior in outdoor and mobile environments has remained largely unexplored. We have performed experiments to bridge this knowledge gap by empirically measuring the performance of an 802.11b system in a broad spectrum of emulated environments. The goal of our work is to contribute to the evolution of currently existing wireless standards by measuring the effects of different channel phenomena on 802.11b. Our results show that current implementations of the 802.11b standard may not be well suited to use in a mobile environment, but that they could conceivably be modified to have better performance in such situations.

Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper presents a novel flexible decoder architecture for irregular LDPC codes that supports twelve combinations of code lengths -648, 1296, 1944 bits- and code rates- 1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.

Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area

In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths, several LDPC decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion: hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine the multi-rate LDPC decoder architecture with the best tradeoff in terms of area cost, error-correcting performance, and decoding throughput. The prototype architecture of this decoder is implemented on an FPGA

Soft Sphere Detection with Bounded Search for High-Throughput MIMO Receivers

We propose a soft sphere detection algorithm where search-bounds are determined based on the distribution of candidates found inside the sphere for different search levels. Detection accuracy of unbounded search is preserved while significant saving of memory space and reduction of latency is achieved. This probabilistic search algorithm provides significantly better frame-error rate performance than the soft K-best solution and has comparable performance and smaller computational complexity than the bounded depth-first search method. Techniques for efficient and flexible architecture design of soft sphere detectors are also presented. The estimated hardware cost is lower than the hardware cost of other soft sphere detectors from the literature, while high detection throughput per channel use is achieved.

Chip-level LMMSE equalization for downlink MIMO CDMA in fast fading environments

In this paper, we consider linear MMSE equalization for wireless downlink transmission with multiple transmit and receive antennas in fast fading environments. We propose a new algorithm based on the conjugate-gradient algorithm with enhanced channel estimation. In order to be robust to the channel variations, the channel coefficients are estimated by using a weighted sliding window. Two methods to determine optimal weights with respect to the Doppler frequency are proposed. The algorithm has been simulated in a fast fading environment (vehicular A with a velocity for the mobile station of 120 km/h). We show by simulations that good performance is obtained in a correlated fast fading environment with reasonable complexity. Moreover, this approach outperforms methods based on basic sliding window or forgetting factor and the LMS algorithm.

Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture

Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbolvector. Detection accuracy of unbounded breadth-first candidatesearch is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms, while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.

Configurable LDPC Decoder Architectures for Regular and Irregular Codes

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3,6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths − 648,1296,1944-bits and code rates-1/2,2/3,3/4,5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.

A General Hardware/Software Co-design Methodology for Embedded Signal Processing and Multimedia Workloads

This paper presents a hardware/software co-design methodology for partitioning real-time embedded multimedia applications between software programmable DSPs and hardware based FPGA coprocessors. By following a strict set of guidelines, the input application is partitioned between software executing on a programmable DSP and hardware based FPGA implementation to alleviate computational bottlenecks in modern VLIW style DSP architectures used in embedded systems. This methodology is applied to channel estimation firmware in 3.5 G wireless receivers, as well as software based H.263 video decoders. As much as an llx improvement in runtime performance can be achieved by partitioning performance critical software kernels in these workloads into a hardware based FPGA implementation executing in tandem with the existing host DSP.

Architecture and Algorithm for a Stochastic Soft-output MIMO Detector

In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detection-decoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.

ASIP architecture implementation of channel equalization algorithms for MIMO systems in WCDMA downlink

The paper presents a customized and flexible hardware implementation of linear iterative channel equalization algorithms for WCDMA downlink transmission in the 3G wireless system with multiple transmit and receive antennas (MIMO system). Optimized (in terms of area and execution time) and power efficient application specific instruction set processors (ASIPs) based on a transport triggered architecture (TTA) are designed that can operate efficiently in slow and fast fading, high scattering environments. The instruction set of TTA processors is extended with several user-defined operations specific for channel equalization algorithms that dramatically optimize the architecture solution for the physical layer of the mobile handset. The final results of the presented design-space exploration method are ASIPs with low cost/performance ratios. Automatic software-hardware codesign flow for conversion of C application code into gate-level hardware design of ASIP architectures is also described. Implemented ASIP solutions achieve real time requirements for the 3GPP wireless standard (1xEV-DV standard, in particular) with reasonable clock speed and power dissipation.