Alexandre de Baynast

Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area

In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths, several LDPC decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion: hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine the multi-rate LDPC decoder architecture with the best tradeoff in terms of area cost, error-correcting performance, and decoding throughput. The prototype architecture of this decoder is implemented on an FPGA

A Systematic Construction of LDPC Codes for Relay Channel in Time-Division mode

We address the problem of low density parity-check (LDPC) code design for relay channel in time-division mode based on a distributed strategy: In the first time slot, the source transmits part of the codeword. The relay and the destination receive it but only the relay can decode it. In the second time slot, the relay transmits the additional redundant bits to the destination. The destination is able to decode the transmitted codeword based on the data received in both time slots. The asymptotic performance of the LDPC codes that we designed are as close as 0.6 decibel from the theoretical limit.