Preetam Charan Anand Tadeparthy

Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps

Sample and hold circuits (SHC) form the front-end circuitry for the switched capacitance pipeline or successive approximation register A/D converter (ADC). The linearity obtained from SHC directly impacts the overall linearity obtainable from the A/D converter. In this paper we describe a new technique for the input-sampling network. Open loop gain and settling time have been optimized for maximum linearity. We also propose a novel architecture to resolve the closed loop pole-zero problems. Linearity as high as 100 dB at a clock speed of 80 MHz was achieved.

A CMOS bandgap reference with correction for device-to-device variation

A circuit technique for compensating the device-to-device variation in bandgap voltage references is presented. The circuit senses the variation of V/sub be/ of the transistor with process and pumps into the emitter a PTAT current in direction opposite to the variation to bring it back to the right value. It also exploits the temperature coeff. of MOS V/sub t/ to compensate for higher order temperature variations. Silicon results show a variation of 60 mV across different lots and less than 50 PPM across temperature (-40/spl deg/ to 130/spl deg/C). The prototype was built in a 0.18u CMOS digital process with low /spl beta/ PNP transistors.

A 115mW 12-bit 50 MSPS pipelined ADC

High sampling rate ADCs are needed in several communications applications like cable modems, and wireless LANs. In this paper we present a low power pipelined ADC cell implemented in a 0.18 /spl mu/m digital CMOS process. The ADC uses a 4-bit/stage architecture for reduced power and area. The ADC has been put on a test chip to verify performance and achieves -70dB THD performance for 10 MHz input at 50 MHz sampling rate.

Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area

The paper presents the design of a 10-bit, 80 MSPS current steering D/A converter (DAC) using only digital thin-oxide CMOS transistors. A large part of the design is automated reducing the design cycle time. To combat systematic gradients on the wafer, we propose using global combinatorial optimization techniques such as simulated annealing and genetic algorithms to obtain a nearly optimal randomized array without any additional area penalty. Additionally, a simple yet elegant technique is used in the current-to-voltage conversion amplifier following the DAC to improve its phase margin in the presence of process variations without expending extra power. The DAC fabricated in a 0.13 micrometre digital CMOS technology shows an INL and DNL of 0.4 and 0.5 LSB respectively, an SFDR of greater than or equal to 70 dB, occupying 0.26 mm/sup 2/ and expending 1.25 mA static power.

Single amplifier bi-quadratic filter topologies in transimpedance configuration

Active-RC configurations, implemented as cascaded bi-quadratic sections (biquads), are the filters of choice for low distortion applications in the base-band. For low power and area applications, single amplifier biquads are best, and are well studied in literature. However, in many applications the input signal is in current domain while the output is a voltage. Output of a current steering digital-analog converter, and output of a down-conversion mixer, are two such examples. In this paper, the authors propose two generic classes of single amplifier bi-quadratic low-pass filter topologies, achieving a second order roll-off in transimpedance (-to-) configuration. Both these topologies are derived with the constraint of fully differential signal processing. The transimpedance active-RC configurations presented here eliminate redundant current-voltage-current conversion and hence provide immense advantages in terms of noise and linearity.

An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]

This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The op amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350 MHz while driving a 2K resistor load and a 3.5 pF capacitive load consuming much lower power when compared to the conventional Miller compensation technique or cascode compensation technique. The op amp was designed in a 0.15-/spl mu/m CMOS technology and achieves a THD of 70 dB for a 30 MHz signal and consumes a total power of 4 mW of a 1.35 V supply.