Gaurav Chandra

A current mode 2.4 GHz direct conversion receiver

A novel direct-conversion RF architecture is proposed that has a current mode interface between the low noise amplifier (LNA) and the down-conversion mixer, as well as the mixer and the base-band filter. The proposed architecture eliminates the voltage swing at the output of all the radiofrequency blocks. The voltage swing is seen only in the baseband after second order filtering, thus resulting in significant linearity improvements and robustness to adjacent channel interference. The current mode interface between filter and mixer also eliminates a redundant voltage-current conversion, giving significant noise advantages. A prototype wireless local area network (WLAN) receiver was designed and simulated in 0.13 /spl mu/m technology, giving a third-order input-referred intercept point of 5 dBm and a noise figure of 2.7 dB for the receive chain. The circuit (including base-band) consumes 8 mA from a 1.2 V supply.

On the Spectral Tones in a Digital-Analog Converter Due to Mismatch and Flicker Noise

Spurious-free dynamic range (SFDR) is one of the most important design metrics for a high-performance digital-analog converter (DAC). SFDR is limited by both dynamic (switching) and static (mismatch) nonlinearities. A good design needs to ensure that the spurious spectral tones caused by the static mismatches do not limit the performance. Aggressively scaling device sizes have also aggravated the problem of flicker noise, which gets modulated by the signal and presents itself as spectral tones. Typically, time domain statistical simulations are needed to guarantee system performance in presence of these nonidealities. In this work, we present a theoretical approach to compute these spectral tones.

A 6mW 480MHz continuous time ΣΔ modulator with 65dB DR over 5MHz bandwidth in 65nm CMOS

A second order, single-bit CT ΣΔ ADC with 480MHz sampling frequency and 5MHz input signal bandwidth is presented. The ADC achieves 65dB DR in 65nm standard digital CMOS technology. The proposed implementation has a highly optimized quantizer, feedback path and clock circuitry leading to 4mA of current consumption and 0.11mm of area. The Figure of Merit for the design is 0.478pJ/conv.

Single amplifier bi-quadratic filter topologies in transimpedance configuration

Active-RC configurations, implemented as cascaded bi-quadratic sections (biquads), are the filters of choice for low distortion applications in the base-band. For low power and area applications, single amplifier biquads are best, and are well studied in literature. However, in many applications the input signal is in current domain while the output is a voltage. Output of a current steering digital-analog converter, and output of a down-conversion mixer, are two such examples. In this paper, the authors propose two generic classes of single amplifier bi-quadratic low-pass filter topologies, achieving a second order roll-off in transimpedance (-to-) configuration. Both these topologies are derived with the constraint of fully differential signal processing. The transimpedance active-RC configurations presented here eliminate redundant current-voltage-current conversion and hence provide immense advantages in terms of noise and linearity.