Priyanka Jain

On the performance of energy detection-based CR with SC diversity over IG channel

ABSTRACT Cognitive radio (CR) is a viable 5G technology to address the scarcity of the spectrum. Energy detection-based sensing is known to be the simplest method as far as hardware complexity is concerned. In this paper, the performance of spectrum sensing-based energy detection technique in CR networks over inverse Gaussian channel for selection combining diversity technique is analysed. More specifically, accurate analytical expressions for the average detection probability under different detection scenarios such as single channel (no diversity) and with diversity reception are derived and evaluated. Further, the detection threshold parameter is optimised by minimising the probability of error over several diversity branches. The results clearly show the significant improvement in the probability of detection when optimised threshold parameter is applied. The impact of shadowing parameters on the performance of energy detector is studied in terms of complimentary receiver operating characteristic curve. To verify the correctness of our analysis, the derived analytical expressions are corroborated via exact result and Monte Carlo simulations.

Unified Recursive Structure for Forward and Inverse Modified DCT/DST/DHT

Abstract This paper proposes implementation of the Modified Discrete Sine Transform (MDST) and Inverse MDST (IMDST) using recursive structures. The formulae required for recursive structures have been derived. Discrete Hartley Transform (DHT), a real-valued transform, is closely related to Discrete Fourier Transform (DFT) of a real-valued sequence and hence its use as an alternative to the Fourier Transform avoids complex arithmetic. This paper presents Modified Discrete Hartley Transform (MDHT)/Inverse MDHT (IMDHT) using Modified Discrete Cosine Transform (MDCT)/ Inverse MDCT (IMDCT) and MDST/Inverse MDST (IMDST) recursive structures. The proposed structures are used for simultaneous computation of MDCT/MDST/MDHT of length N (divisible by four) and their Inverse (IMDST/IMDHT). The proposed structures are parallel, simple, regular and therefore highly suitable for VLSI implementation.

Regressive Structures for Computation of DST-II and Its Inverse

Efficient regressive structures for implementation of forward (DST-II) and inverse discrete sine transform (IDST-II) are developed. The proposed algorithm not only minimizes the arithmetic complexity compared to the existing algorithms (Wany (1990), Hupta and Rao (1990), Yip and Rao (1987), Murthy and Swamy (1992)) but also provides hardware savings over the algorithm (Jain et al. (2008)) by the same authors. The naturally ordered input sequence makes the new algorithms suitable for on-line computation.

An Efficient Approach for Realization of Discrete Sine Transform and its Inverse

Abstract In this paper, novel very-large-scale integration (VLSI) algorithms for computing the Discrete Sine Transform (DST) and its inverse (IDST) are proposed. By respectively folding the inputs, the DST kernels are derived to realize it through Infinite-impulse response (IIR) structure. Single folding algorithm provides data throughput two times of that achieved by the conventional methods. The double folding recursive algorithms for DST and IDST have been suggested, which reduce the computation cycles to one forth of that in the single folding method. Moreover, the regular and modular properties of the proposed recursive structures are easily amenable to VLSI implementation.

Performance of MRC receiver over Hoyt-lognormal Composite Fading Channel

ABSTRACT In this article, mixture gamma (MG) distribution is used for analysing the performance of L-Hoyt/lognormal composite fading channel. To overcome small-scale fading effect, micro-diversity using maximum ratio combining (MRC) is used at the receiver. Due to mathematical complexity, performance analysis of composite (L-Hoyt/lognormal) fading models is not present in closed form. The analytical expressions for the performance measure are derived in the form of received signal-to-noise ratio (SNR). The impact of system parameters on the energy detector (ED) performance is studied in terms of receiver operating characteristic (ROC) and area under the ROC curve (AUC). Further, the detection threshold parameter is optimised by minimising the total probability of error for L-Hoyt/lognormal channel. The accuracy of the proposed closed-form expressions is validated by comparing all the results with the Monte-Carlo/exact simulations.

An experimental study of wireless transceiver of modulation schemes using Software Defined Radio

SDR is nothing but software defined radio technique using laboratory virtual instrument engineering workbench (LabVIEW) as software to mark the radio utilities hardware implemented i.e. universal software defined radio (USRP). In the advancement of SDR implemented LabVIEW to develop as instrument that offers function to support SDR. SDR is the root of innovative wireless communication environment that support both types of fading i.e. short term and long term even composite fading too to create realistic scenario. USRP was a device to develop as a high speed, lower cost and user friendly SRD platform. This paper presents the experimental implementation of LabVIEW and USRP for mounting software and hardware based wireless channel transmission and reception environments for different modulation scheme as constellation diagram, eye diagram and bit error rate (BER), transmitting from TX1 of USRP1 to receiving at RX1 at USRP2. USRP, Software Defined Radio are RF software programmable radio transceiver designed for wireless communication environments.

FPGA-Based Architecture for Implementation of Discrete Sine Transform

This paper presents architecture for discrete sine transform (DST) algorithm using VHDL description and its implementation on field programmable gate array (FPGA). Several algorithms have been proposed to implement the DST in its recursive structure form and focus on minimizing the number of additions and multiplications. The hardware designs of the algorithms are largely ignored. The implementation of DST algorithm on the FPGA is motivated by the fact that large memory FPGAs are now available providing a platform for processing real-time algorithms on application-specific hardware with substantially higher performance.

Extraction of Equivalent Circuit Parameters of Metamaterial-Based Bandstop Filter

This article presents the design and analysis of a metamaterial-inspired Bandstop Filter (BSF) providing suppression of frequency at 3 GHz. The overall size of the proposed BSF is 20 mm × 20 mm × 1.6 mm. This paper presents the extraction of lumped parameters of the designed BSF using simulated results and validation of the results using equivalent circuit simulation has also been presented. The analysis is performed using transmission coefficient, reflection coefficient, and impedance curve.

Metamaterial-based Patch Antennas—Review

Metamaterials have gained a huge interest in research area due to their extraordinary electromagnetic properties. Metamaterial can be used to overcome disadvantages of patch antenna such as size reduction with acceptable amount of bandwidth and power. This paper gives a brief introduction and classification of basic metamaterial structures and their usage in antenna engineering. The applications of these structures in enhancement of various antenna properties are also discussed. The paper also describes their advantages over conventional antenna structures. Major objective is to analyze the best configuration required while designing the antenna that suits the desired specification and helps in developing the future ideas by utilizing the advantages of the available structures.

Realization of Recursive Algorithm for One-Dimensional Discrete Cosine Transform and Its Inverse

In this paper, recursive algorithm for the computation of discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) has been proposed. This algorithm has been implemented using recursive structure, i.e., infinite impulse response (IIR) filter. Further, any desired output kernel can be computed independently which is an added attraction of the proposed design. Besides being recursive, this algorithm requires less multiplier and adders than other DCT algorithms. The suggested scheme is time efficient as it provides output in N/2 computational cycles, where N is the length of the input sequence. Therefore, the proposed algorithm is both time and hardware efficient. Further, the recursive property of proposed algorithm results in a regular and modular structure which results in easier VLSI implementation.